Imperas debuts Cortex-A15/R4 Fast Processor Models - Embedded.com

Imperas debuts Cortex-A15/R4 Fast Processor Models

Imperas has released its models of the ARM Cortex-A15, Cortex-R4, Cortex-R4F and ARM1176 processor cores. The models, together with the OVP and Imperas M*SDK tools were demonstrated at the ARM TechCon 2012 conference in Santa Clara, Ca.

These models, as with all OVP models of the ARM processor cores, are now available from Open Virtual Platforms™ (OVP). Support from OVP includes example virtual platforms incorporating the cores, with the processor core models also supported in Imperas’ advanced software development tools.

The new models of the ARM processor cores, as well as models of the other ARM processors including the ARM7, ARM9, ARM10, ARM11 and Cortex-A, Cortex-R, and Cortex-M families, work with the Imperas and OVP simulators, and have shown exceptionally fast simulation performance of hundreds of millions of instructions per second.

The OVP Fast Processor Models include support for both the 32 and 16-bit instructions, as well as the MMU, MPU, TCM, VFP, NEON, TrustZone, virtualization and Large Physical Address Extension (LPAE) features. The OVP Fast Processor Models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/ARM.

According to Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative, all OVP processor models are designed to be instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle.

He said OVP processor models employ a state of the art just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP models.

The native TLM-2.0 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

OVP also has reference virtual platforms incorporating the ARM cores, including a virtual platform of the ARM Versatile Express development board using any of the ARM Cortex-A family of models. These reference platforms are all available as source code, and are easily modified to add or change the memory and peripheral components to customize the platform as required for software development.

In addition to working with the OVP simulator OVPsim, the OVP Fast Processor Models work with the Imperas Software Development Kit (M*SDK), which includes advanced tools for multicore software verification and analysis as well as key tools for software development on virtual platforms such as OS and CPU-aware tracing (instruction, function, task, event), hot-spot profiling, code coverage and memory and cache analysis.

The Verification, Analysis and Profiling (M*VAP™) tools utilize the Imperas SlipStreamer patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

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