Implement PCI Express 1.1 in your latest design -

Implement PCI Express 1.1 in your latest design


Don't be scared off by the latest changes to the specification. By following a few straightforward steps, you're sure to comply.

What do you need to know about physical-layer compliance measurements under the PCI Express 1.1 specification? Significant changes in jitter and phase-locked loop (PLL) bandwidth were instituted with this revision of the PCI Express 1.0a specifications. Yet, perhaps the most important point to remember is that the PCI-SIG (the governing body of PCI Express) will soon require enforcement of the PCI Express 1.1 standard for vendors who wish to have their products listed on the PCI-SIG's PCI Express Integrators List.

PCI Express (PCIe) is the next-generation evolution of the PCI interface bus that's the dominant I/O interconnect found in today's desktop, server, and mobile computing platforms. The bus currently operates at 2.5 Gbits/s across up to 16 lanes, providing a maximum transfer rate of 40 Gbits/s. While deployment of PCIe 2.0 (at 5 Gbits/s) is just beginning, the majority of today's add-in card and motherboards deploy various flavors of PCIe interfaces operating at the 2.5-Gbits/s rate.

Wide implementation of PCIe didn't happen by accident. The authors of the specification and the PCI-SIG board of directors worked hard to ensure that products bearing the PCIe logo met a consistent level of performance and quality. The reason for this is simple—when you buy a PCIe product from one vendor you expect it to work without reservation with other products as its designers intended. This consistent and reliable interoperability is key to adoption of any standard interface.

As a designer who intends to use PCIe in your product, one of your key responsibilities is to respect the PCI standard and work to ensure that design complies to its electrical and transactional requirements. Interoperability starts at the physical layer with well-designed transmitters, receivers, transmission lines, and interconnects.

When PCIe 1.0a was introduced in 2004, the specification was considered well wrung out and in final form. Later, the PCI-SIG discovered some problems. It discovered that some of the devices that had passed the compliance tests didn't interoperate. The PCI-SIG investigated and discovered that some parts of the 1.0a specification needed to be tightened up, and so additional refinements to the compliance-testing procedures were made. These changes led to the 1.1 version and are summarized here:

The PCIe base specification covers the requirements for transmitter and receiver silicon devices. The Card Electromechanical (CEM) specification covers actual motherboards and add-in cards that use PCIe silicon. The CEM specification is a subset of the base specification and focuses on measurements made at the interface connector as opposed to pins (or BGA balls) of PCIe devices.

Base spec changes
The 1.0a clock-recovery function for jitter analysis approximated a third-order filter response. This filter response gave you a single test procedure for add-in cards and motherboards. It also worked when spread-spectrum clocking (SSC) was enabled or disabled. The SIG discovered that if your system had excessive low-frequency jitter, the jitter could be masked by this aggressive filter. Interoperability problems could then be a significant risk.

Thus, in the 1.1 specification, three significant changes related to jitter analysis were made to the clock-recovery requirements. Under the 1.1 spec, you'll now use a first-order clock-recovery filter, you'll measure jitter using a clean reference clock, and you now must meet a tighter jitter limit and eye mask (compared with the 1.0a spec). You're also expected to measure jitter over a population of one million unit intervals.

The SIG also discovered that the loop bandwidth of a receiver's PLL wasn't specified in the 1.0a specification. This hole was fixed under the 1.1 spec by limiting a receiver's loop bandwidth to between 1.5 and 22 MHz, with a peaking of no more than 3 dB.

CEM spec changes
Under the 1.0a specification, jitter was specified as a total jitter value. Under the 1.1 spec, the jitter budget has been decomposed into both random jitter and deterministic values. For compliance purposes, you'll only need to pass a total jitter (or TJ) limit. The jitter budgeting adds room for reference-clock phase jitter, which wasn't expressly characterized and limited in version 1.0a.

As a result, when it comes to compliance testing your silicon or an add-in card design, you must:

  • Measure jitter using a clean reference clock.
  • Measure jitter over one million unit intervals.
  • Use the new jitter values and eye diagram limits.
  • Test your receiver's PLL bandwidth for compliance.

If you're designing a motherboard, it's not practical to inject a clean reference clock into your system. So you will likely see significantly greater jitter if you use the new 1.1 method for clock recovery. You can optionally use the old 1.0a method and the new jitter and mask limits. Also, if you can't disable spread spectrum clocking (SSC) on your motherboard, you must use the 1.0a clock-recovery method to filter out the low-frequency jitter caused by SSC modulation. Thus, your requirements under the 1.1 specification are to:

  • Measure jitter using the standard motherboard reference clock.
  • Measure jitter over one million unit intervals.
  • Use the 1.0a or 1.1 method for clock recovery (1.0a must be used if SSC can't be disabled).
  • Use the new jitter values and eye diagram limits.
  • Measure your reference-clock phase jitter.

Reference-clock phase jitter
The PCI-SIG has now placed limits on your receiver's PLL and the phase jitter on your motherboard's reference clock. The reason is that if your transmitter and receiver's PLL have an identical loop bandwidth response, the jitter transferred from the system's reference clock won't matter as it'll be substantially removed. However, you can't count on this always being the case. In fact, it isn't very unlikely to occur unless you have total control over both the transmitter and the receiver.

The 1.1 specification permits a loop bandwidth between 1.5 and 22 MHz (with up to 3 dB peaking). The worst case scenario is to have a transmitter's PLL bandwidth be 1.5 MHz and a receiver's PLL bandwidth be 22 MHz (or vice versa). In this case, jitter on the reference clock that falls within the 1.5- to 22-MHz frequency spectrum will transfer (called the jitter transfer function ) over to the high-speed data lines. Because of this, the 1.1 spec limits how much jitter exists on the reference clock within the 1.5- to 22-MHz spectrum to 86 ps (at 10- to 6-bit error rate).

To measure the phase jitter on your reference clock, three things must be done. First, you must measure your clock's period error using a trend function. Second, you must filter that period error trend using a very specific bandpass function defined in the CEM spec and shown in Figure 1. Finally, once you've filtered the trend data, you must measure the maximum jitter that's in the 1.5- to 22-MHz band. Fortunately, the PCI-SIG provides a utility function on its web site (called Clock_Jitter_Tool ) that takes the trend data captured on your oscilloscope and performs the proper filtering function. Members can obtain this tool from the organization's web site at

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Passing the 1.1 measurements
To help ensure that your product meets the PCIe 1.1 requirements, the PCI-SIG provides software tools, fixtures, and test procedures on its web site. To meet the clean clock requirements for jitter measurements, the SIG offers its members two compliance fixtures, one for add-in cards (such as graphics boards, LAN cards, and host bus adapters for storage) and one for motherboards. The add-in card test fixture is called the >Compliance Base Board (CBB) . It comes with a very low jitter reference clock based on an Epson PECL oscillator and sturdy SMA (SubMiniature version A) connectors that let you measure the jitter on your transmitter.

For PCIe 1.1, the compliance load board (CLB) is the same as was used under the 1.0a spec, as no changes were necessary. Nevertheless, you'll want to add a compliance load to your CLB to accurately measure your motherboard reference clock. The compliance load is added by soldering two 2-pf capacitors near the header pin where the reference clock is probed on the CLB, as in Figure 2.

Transmitter compliance
An advantage of PCIe over previous multiple-gigabit interfaces is that it can generate a continuous repeating pattern without having to connect any external test equipment, which lowers the cost of test. The easiest and most reliable way to measure jitter is to measure it on a repeating continuous pattern. With PCIe, you don't need a gigabit-capable pulse generator to drive a signal into your device, nor are you forced to figure out how to put your PCIe device into a loop-back mode just to measure transmitter jitter. The device should generate a specific continuous compliance pattern (most commonly a 40-bit pattern) by connecting the device to a compliance test fixture. Note that if you're only testing just silicon, getting the device into compliance mode may require register modifications or other low-level manipulation.

When you attend a PCI-SIG sponsored workshop, the first thing the SIG reps do is test to see if your device can output a valid compliance pattern. Most engineers take this for granted but be forewarned, about 10% to 20% of the devices I've personally tested at workshops fail for the following reasons:

  • The pattern isn't generated at all.
  • The device attempts to train when placed in the compliance fixture.
  • The compliance pattern contains illegal symbols (not allowed in the pattern).
  • The generated compliance pattern has incorrect disparity.

One way to test your compliance pattern is to use an 8b/10b decoding function on your oscilloscope. One popular family of scopes offers an optional serial data analysis software package that, among other things, provides decoding, triggering on symbols, and symbol search capabilities. This can make decoding an 8b/10b data stream as simple as pressing a few buttons.

Once you know that your device is outputting a valid compliance pattern, the next step is to measure its jitter. The PCI-SIG provides a tool called Sigtest that measures jitter and provides an eye diagram. Sigtest is the tool that will test your device at a PCI-SIG sponsored workshop. It's easy to use and requires only that you save a captured waveform from your oscilloscope to a standard file format (typically a .CSV format) that most scopes support.

Another option is to use a test-equipment vendor's dedicated compliance pattern. The reason why you might want to purchase one of these tools versus relying on the SIG's free Sigtest utility is that Sigtest is a simple pass/fail tool offering limited capability to debug failures. If your device fails a particular compliance test you have to figure out why. I suggest you look at some of the industry's PCIe compliance tools as a next step.

Once you complete those tests, you'll want to share those results with other team members or with your silicon or IP vendor if you discover a problem. An oscilloscope is often used to show how a device meets or doesn't meet its design parameters. When looking at tools, you want to ensure the tool you choose can produce unambiguous compliance-test results that are easy to share with others. Often unambiguous means that in addition to just a reported number (like rise time or common mode voltage), you'll want to be able to share the wave form from which that parameter was derived.

Measuring reference-clock phase jitter
To measure the phase jitter on your reference clock, create a measurement trend of the clock-period error. For PCIe, the 100-MHz reference clock has a 10-ns period. Ideally, every clock period should measure exactly 10 ns, but for various reasons including noise coupling, temperature shift in the crystal oscillator, non-ideal amplifier performance, and other factors, the clock period will vary over time. Your oscilloscope can capture this trend information in its acquisition memory. You can either capture the trend as a single acquisition, or, if you want a more statistically valid result, capture multiple acquisitions.

If you capture multiple acquisitions, you must carefully concatenate the acquisitions so as to not introduce significant discontinuities in the final record that's used for analysis. One vendor has implemented a phase jitter measurement for PCIe reference clocks that lets you measure your reference clock's phase jitter for the specified one million unit intervals. This software uses a clever intelligent stitching algorithm that applies a hamming or windowing function to the acquired data to ensure that the each record begins and ends at the same point in the SSC Cycle (see Figure 3).

Once each of the data records are windowed, each 180-degree cycle is cached in memory. Multiple acquisitions continue to build the memory cache until eventually the user's specified number of unit intervals have been acquired. The cached data sets are then concatenated, the appropriate phase-jitter filters are applied, and the jitter measurements performed. The software reports the phase jitter of your reference clock for one million unit intervals or more, depending on what value you specify for the size of your desired statistical sample.

Rick Eads is a program manager for serial bus applications for high-performance oscilloscopes at Agilent Technologies. He currently represents Agilent on standards committees for PCI Express, ExpressCard, and FB-DIMM and manages the PCI-SIG's Gold Electrical suite at PCI-SIG sponsored workshops. He holds both a BS in electrical engineering from Brigham Young University and an MBA from the University of Colorado. He can be reached at .

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