Implementing a multi-peripheral controller using a tiny mixed-signal FPGA -

Implementing a multi-peripheral controller using a tiny mixed-signal FPGA


As you may recall from previous columns, I tend to think of Silego's GPAK chips as being super-small mixed-signal FPGAs that you can literally design and program in just a few minutes, and that cost only a few cents each.

Well, the folks at Silego were so excited by the interest my columns generated within the and communities that they decided to offer 25 development kits for free (see Want a free Silego GPAK4 mixed-signal FPGA development kit?).

The idea was that and community members would email me to excite me and delight me with descriptions of the amazing hobby or work projects they might use GPAK4 devices for, thereby convincing me that they deserved to receive one of these little beauties.

Two weeks later, I sauntered into the Pleasure Dome (my office), ensconced myself in my Supreme Commander's Chair with its super-soft cuddly cushion, and selected the 25 entries that most ignited my imagination and whipped my creative juices into a frenzy (see 25 Free Silego development kits will soon be winging their way).

After this, things went quite for a while, until earlier today when I heard from one of the lucky recipients, J.R. Stoner, who is principal engineer (and self-described “chief bottle-washer”) at the Bifrost Development Group.

In his email, J.R enclosed the .gp4 (GPAK4) design file associated with his latest project, which is a multi-peripheral controller (click here to download a compressed ZIP file containing the .gp4 design file along with the images presented below). The schematic for the portion of the design featuring the GPAK4 chip (a 20-pin SLG46620 device) is shown below.

(Click here to see a larger version of this image.)

J.R. tell me that he's verified both the digital and analog functions in simulation — using Silego's free GreenPak Developer application — and he's now working on the actual hardware. The graphical interface used to capture the design and screenshots of some of the simulation results are shown below.

(Click here to see a larger version of this image.)

Quadrature Up
(Click here to see a larger version of this image.)

Quadrature Down
(Click here to see a larger version of this image.)

SPI Counter Up
(Click here to see a larger version of this image.)

Theory of operation
J.R. says that the logic is related to a common XOR method of quadrature decoding, plus the input signals are synchronized to the oversampling clock. The SPI output for both the fan PWM and the quadrature up/down counter have been confirmed at the pin level. The up/down DIR selector is derived from the XOR of one of the quadrature phases (A) and the latched other phase (B).

The four-input XOR is an odd-parity generator connected to both synchronized phases — and their latched equivalents — through the final pair of D flops. This is used to generate the FSM0 counter clock pulses, one for each of the four phase transitions per unit of the quadrature signal. The latch clock for DFF 1 is derived from the 25 kHz RC clock, so each phase transition (STEP) pulse width is 40 µs.

Each time a quadrature cycle is detected, the SPI counter will increment or decrement by four, which is then read out the SPI serializer as the MSB (most-significant bit). The intention is to measure all phase transitions in the SPI counter, stripping off the two LSBs (least-significant bits) of the count, thereby reducing the sampling noise by 12dB.

The /SWIN to SWOUT unit is a simple de-bouncer for the UI selector for this project.

The analog-to-digital converter (ADC) reads the temp sensor, which is loaded directly into the LSB of the SPI serializer. DLY7 is a ring oscillator delay of 7.22 µs to eliminate startup glitch from the sweep count during ADC startup. And CNT8 is a period sweep counter, which is used to gate the PWM unit.

Advantages of the GPAK4
J.R. also says that one could envisage a simpler hardware implementation involving feeding A, B, and SWxx to the MCU's GPIO pins (of which not many are available) coupled with an external DAC circuit (which would have to be used for the thermistor).

However, the GPIO pins would have to be software de-bounced, while the DAC would consume yet more I/O pins. Then separate ISR (interrupt service routines) — or clocked polling — would have to be written to handle the devices at a level that would consume too much time resources from the main CPU.

The biggest wins in using the GPAK4 device for these functions are (a) simplification of the interfaces to a single SPI channel, (b) intrinsic de-bounce of the mechanical inputs, (c) automatic conversion of the analog thermistor signal to a 12V PWM fan, and most importantly (d) complete asynchrony between the quadrature input device and the SPI register, which provides not only an up/down counter for the encoder, but also a non-interrupt way of detecting over-temp on the thermal sensor. Also, there is significant simplification of the board layout using one itty-bitty 4mm device.

But wait, there's more…
Well, I hope there's more LOL. I am really impressed with what I see here. Not only has J.R. used his GPAK4 development kit to implement a real-world solution, he's provided sufficient into the design to allow the rest of us to stand on his shoulders, as it were.

In the coming weeks and months, I'm hoping some of the other recipients of the GPAK4 dev kits will share the projects they've been working on using the material provided by J.R. as the standard to meet or beat (but no pressure LOL). In the meantime, what do you think of J.R.'s GPAK4 application?

6 thoughts on “Implementing a multi-peripheral controller using a tiny mixed-signal FPGA

  1. “MaxnnDid you see my inclusion of Silego in my recent blog on Timers.n–anyone–“

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  2. “I hadn't seen that (running around like a chicken without a head) — but I just went over to read it — very interesting — I hadn't realized there was so much happening in timer space!”

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  3. “Unfortunately, all I've had time to do is open the box and check that everything is there. One of these days I really need to find time to work on some of these projects….n”

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  4. “I have every faith that one day you will leap to your feet and say — “This design I'm about to start working on would be perfect if implemented in a GPAK4…”nnI await in dread anticipation LOL”

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  5. “Yes, that is what I had in my head for some while after receiving the dev kit. My first impetus for it was to design a power startup sequencer for an A13/A20 controller, but it was just too much to totally eliminate the external “jelly beans” needed t

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