Implementing an Enhanced Rate Multiplier in your embedded systems design -

Implementing an Enhanced Rate Multiplier in your embedded systems design

In many embedded communications and networking applications it is oftennecessary to derive fractional frequencies from some common baselinefor use in particular applications.

In communications receivers, the fractional frequency is needed asoverhead bits or partial data streams are removed. In the transmitters,the lower frequency clocks are required to manipulate data as over headbits or other data streams are added.

Consider, for example, the design of a fractional-NPLL for amultiplexer/de-multiplexer(MUX/DEMUX),which is digitally connected to a telephone central office at 56Kbits/second (US) or 64 Kbits/second (European), in which the primaryclock rate was therefore 56 K or 64 K, from which it is necessary togenerate output data rates of 300, 600, 1200, 1800, 2400, 3600, 4800,7200, 9600, 14400, 19200, 28800, and 38400 kb/sec, respectively.

Complicating such a design is the need to make the MUX/DEMUXcascadeable, because the input frequency could be any one of thefrequencies listed above, and the need to verify every combination andfrequency.

Because of such complications, the fractional-N PLL approach hasbeen replaced in many designs with the Enhanced Rate Multiplier (ERM).The advantages claimed for the ERM approach are that it:

* consumes less power, important in battery powered devices
* requires less silicon
* is easier to design, test and verify
* does not have a limited pull-in range of frequencies
* does not suffer from the vagaries of process, voltage and temperaturevariations

In this article we will discuss the details of building an ERMapplication in software in both Java andVerilog and provide downloadsof the actual code to be used.

Binary and enhanced rate multipliers
As will be shown, the ERM consists of a single divider whose size isthe same as one of the two dividers used in the Fractional-N PLL.Therefore, the first two claims are easily satisfied, since the PLL andone PLL divider has been eliminated.

Since this is an all-digital design, the last three claims are alsosatisfied. To understand the ERM, we must understand the Binary RateMultiplier (BRM).

Rate multipliers are also known as pulse swallowing circuits. TheEnhanced Rate Multiplier is a systematic method for swallowing anynumber of pulses.

A BRM, such as the SN7497, creates an output signal which is afraction of the input frequency with the denominator a power of 2.Shown in Figure 1 below is aBRM.

Figure1. Four-Bit Binary Rate Multiplier Schematic

A BRM has the following transfer function:

Fout / Fin = N / 2M where M is the number of bits in the binary counter.

A BRM consists of a binary counter, followed by a right-most-1detector, and an OR gate which collects pulses from the right-most-1detector as shown above.

Notice that the numerator bits are in reverse order from thedenominator bits. N3 is ANDed with D0, N2 is ANDed with D1, N1 is ANDedwith D2 and N0 is ANDed with D3.

If N3, the most significant bit, is 1, 1/2 of the pulses are enabledby D0 which is the right-most-1 half of the time.

If N2 is a 1, 1/4 of the pulses are enabled by D1 AND NOT D0. Thesepulses are ORed with the pulses from N3 if N3 is enabled.

If N1 is a 1, 1/8 of the pulses are enabled by D2 AND NOT D1 AND NOTD0. These pulses are ORed the other pulses if they were enabled.

If N0, the least significant bit, is a 1, 1/16 of the pulses areenabled by D3 AND NOT D2 AND NOT D1 AND NOT D0. These pulse are ORedwith the other pulses.

The table below highlights the right-most-1 bit.

The maximum number of pulses for this example is 15/16. Figure 1 suggests that another bit,N4, is a natural extension for an F ou t/F in ratio of 1. This option may berequired in your design.

It is easy to describe how a BRM works and how to program it.However, if the denominator of the frequency ratio is not a power oftwo, the BRM cannot be used without some error. By increasing the sizeof the BRM, the error can be made arbitrarily small, but never zero.This brings us to the ERM.

The Enhanced Rate Multiplier
Changing the binary counter to an ordinary counter and optimizing theright-most-1 detector with bitwise operations creates the “Enhanced Rate Multiplier”. By using an ordinary counter, any modulo can now beachieved. Optimizing the right-most-1 detector makes the ERMparameterizable ie easy to change the implementation size. Figure 2 below is the Four-BitEnhanced Rate Multiplier Schematic.

Figure2. Four-bit Enhanced Rate Multiplier Schematic

The denominator register, DR, in the upper left corner contains thedivisor minus 1. DR is loaded into the decrementing counter when thecounter reaches zero. The borrow bit from the decrementor indicateswhen the counter is zero. The input and the output of the decrementorare D and DD, respectively.

The right most 1 is detected by XORing D with DD, followed by ANDingthe result with D. The XORing identifies the decrementor's changingbits. The changing bits are always contiguous and right-justified. TheANDing with D isolates the right most 1.

ANDing the right most 1 with a bit-reversed N bits yields pulseswhich are ORed to create the desired frequency output.

The N bits can be reversed in hardware or in software. If the bitsare reversed in hardware and the size of the counter increases, theprogramming table must be completely changed. But if the N bits arereversed in software, the programming table is not impacted by sizechanges. Therefore, the bits are reversed in software.

The operation of the ERM is similar to the BRM. When N3 is set, approximately ½ of the pulses are allowed if the modulo is greater than 1.When N2 is set, approximately ¼ of the pulses areallowed if the modulo is greater than 2. And so forth. A Java programis supplied to deal with the approximations and find the N for thedesired fraction.

ERM Verilog Code
The Enhanced Rate Multiplier Verilog code snippet is listed below. Thefive significant lines are bolded with comments to describe itsoperation. This code snippet illustrates that the implementation isvery simple compared to a Fractional-N PLL.

ERM Procedure
The steps to programming the ERM are:

1) Get the input andoutputfrequencies from the system requirements.
2) Divide the input and outputfrequencies by the greatest common denominator (GCD).
3) DR is the input frequencydivided by the GCD minus 1.

Compute the estimate of N, Nest.

Nest = (2** SIZE) * fout /fin , where SIZE is thenumber of bits in DR.
If DR + 1 is a power of 2, Nest isexact.
Usually, Nest is low due totruncation.

5) Through simulation orexperimentation, increment Nest until the desired frequency ratio isachieved.

This tedious procedure is simplified with the supplied Java code.Only step 1 is required – supply the input and output frequencies.

ERM Java Input
The Java input file has the following format.

A valid input is two integers per line, the input frequency and theoutput frequency. Lines that don't begin with two integers are treatedas comment lines. The integers are dimensionless and may representHertz, Kilohertz, Megahertz or Gigahertz.

The integer must fit within 63 bits or about 19 digits. The inputfrequency must be larger than the output frequency. Since eachfrequency pair creates a frequency object which is stored in acontainer, there is no hard limit on the number of frequency pairs.

ERM Java Output
The output has a header describing the program and program requirementsalong with the listing of the inputs and the outputs. The output beginswith “$$$” indicating pay dirt.

The minimum counter size is stated. The input frequency, the outputfrequency, the denominator and the numerator are listed with commaseparators. The hex denominator and the hex reversed numeratornecessary for programming the ERM are listed with spaces separatingevery four nibbles. The output format adjusts to accommodate longintegers.

Notice that HexRateRev islarger for lower output frequencies and smaller for higher outputfrequencies. HexDenom is Denomminus 1.

This UART example emphasizesthat ERM is for embedded systems. WhileERM creates an accurate UART frequency, a user will be bewildered by acryptic table like this one. Also, he will not be able to create a newtable if his crystal frequency changes.

In embedded systems, the system requirements are known and uglyprogramming tables are hidden from the users.

We have a basic understanding of the ERM so it is “just a simplematter of programming” the N and DR of the ERM. We now address threeapplication issues.

ERM Application Suggestions
The size of the implementation can be larger than the minimum sizespecified in the output listing without side-effects.

To create a near-50% duty cycle waveform, follow the rate multiplierby the largest Johnson Counter your system willtolerate. A Johnson counter divides by 2 * N, where N is any integer.

To find the largest Johnson count, divide Fin by Fout and find thenearest lower Johnson count. For example if Fin / Fout is 9.99999, thenext lower Johnson count is 8. A larger Johnson count, as compared tosmaller, will lower the jitter. The input frequency to the Johnsoncounter will be higher and the averaging greater, thus lowering thejitter.

Sometimes the ERM output is periodic; for example, when thefrequency ratio is one third. In some applications, it is desirable tohave some jitter to eliminate spectral spikes. In this case, use twosixths or some other ratio. The denominator can be any multiple ofDenom that fits within the size of the denominator. The Java programcan be modified to display a denominator other than the minimum.

As an aside, some research is required to optimally alter the ERM tospread a spectrum.

ERM Summary
I have described a systematic method to create any rational fractionalfrequency using the ERM. I have supplied the associated verilog codeand the Java program to aid in its implementation and programming. Alltheimplementation barriers have been addressed. If the ERM meets yourneeds, use it freely.

Available in the 2007 Code Archive,the Verilog code for the ERM discussed in this articlecan be downloaded in a Zipfile. The Java code is also available in itsown Zip file, along with the sample files used in thisarticle

Andrew Kameya is senior systemsengineer at Skyworks Solutions,Inc .

1) SN7497 – Synchronous 6-bit Binary Rate Multiplier
2) CD4089B – CMOS Binary Rate Multiplier

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