This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.
A growing number of embedded designs are moving to multicorearchitectures, while virtualisation technology is also moving tomainstream. Going forward, these two disruptive technologies may feedoff each other.
This article will explain some of the history, future hardwaretrends and emerging usage scenarios of hypervisor technology, thendiscuss how multicore architectures improve the usability andefficiency of hypervisors.
The concept of a hypervisor that can host multiple 'guest' operatingsystems on a single hardware platform was pioneered by IBM in itsmainframes more than 30 years ago. IBM used hypervisors to enablelegacy versions of its operating systems to continue to execute on newhardware platforms.
In addition, IBM software developers used hypervisors as aconvenient platform for developing and testing new operating systemfeatures. The following is a list of historical uses of hypervisortechnology:
* Debugging and testing of privileged code/new architectures
* Debugging and testing of software prior to hardware
* Running distinct and legacy operating systems on the same hardware
* Sandboxes for untrusted software
* Consolidation: improved utilisation of a single computer
* Aggregation: improved utilisation of many computers
* Portability: vary hardware, but keep same OS and applications
* Server provisioning: migration, backup, recovery
Despite its obvious utility, hypervisor technology was largelyabsent from mainstream computing until the turn of the millennium when VMwaredemonstrated that virtualmachines could run with reasonable performance on commodity PChardware.
Since then, a variety of hypervisor technologies have come tomarket, including MicrosoftVirtualPC, open source XEN (whose commercial spin-off, XENSource,was recently acquired byCitrix), Linux KVM, Parallels, and Green Hills'PaddedCell. Hypervisor technology was made practical on commodity hardware bya combination of intelligent software and, more recently, hardwareacceleration added into the leading mainstream computer architectures.
In 2005, Intel launched its VirtualisationTechnology (VT) which dramatically improved hypervisorexecutionspeed on Intel Architecture based platforms. Intel has continued to addadditional performance and security features to aid hypervisors. AMDhas followed a similar path.
In the PC world, hypervisors are able to implement 'fullvirtualisation' in which the guest operating systems and theirapplications are able to run unmodifi ed on the virtual machine. In theembedded world, a number of paravirtualisation (modified guest)solutions have been attempted; however, the performance of embeddedmicroprocessors has precluded full virtualisation.
That may be changing.
Recently, Power.organnounced the addition of virtualisation acceleration features into thePower Architecture embedded profi le that may make full virtualisationpractical as implementations come to market in the next couple ofyears.
It is probably a good bet that ARM, MIPS, and other popular embeddedprocessor cores will eventually follow suit. In addition, Intel ispromulgating its virtualisation technology to its embedded-classchipset implementations.
More hardware trends
Intel's VT-d (orDirected I/O) technology recently came to market indesktop chipsets, providing an important addition to the virtualisationacceleration story. AMD and Power Architecture use the term 'IOMMU' forthe same general capability.
Traditionally, hypervisors needed to emulate I/O devices becauseeach guest operating system could not be trusted to have direct accessto DMA and other physical resources which could inadvertently ormaliciously affect other guests.
The hypervisor would intercept and emulate all guest I/O requests,creating a performance bottleneck. With IOMMU, the guest can beprovided direct access to the I/O device (including DMA); thevirtualisation hardware will prevent any I/O access (even from theperipheral itself) from accessing memory outside of the virtualmachine. Another major improvement coming to virtualisation hardware iswhat is referred to as 'extended page tables'.
Traditionally, the hypervisor must intercept every guest attempt tomodify system page tables. The hypervisor maintains a 'shadow pagetable' for each guest, and each guest modifi cation is emulated,accomplishing the desired physical memory partitioning.
In the future, hardware page tables will be extended, adding anadditional level so that guest physical memory references will bemapped to a true physical location programmed by the hypervisor.
Thus, guest page table references will no longer need to beemulated, removing what is arguably the largest remaining performancebottleneck in virtualisation today.
While most hypervisors were created for the sole purpose of hosting oneor more virtual machines, a small number of hypervisors have beendesigned to augment an existing operating system environment withvirtual machine capability.
For example, the Green Hills Padded Cell hypervisor was designedspecifically to execute on INTEGRITY, a secure realtime operatingsystem.
|Figure1: Hybrid-visor architecture|
Unlike traditional hypervisors, Padded Cell runs as a user modeapplication, with a separate instance for each guest environment (Figure 1 above ).
Separation of guest environments is trusted to the secure and safetycertifi ed microkernel, which provides bounded and guaranteed servicesto each guest. In addition, 'native' applications can peacefullycoexist with the guest environments, enabling developers to hostreal-time and/or security-critical applications that cannot be trustedto commodity guest operating systems.
The hybrid-visor architecture enables a number of fascinating usagemodels, many of which provide increased fl exibility and reduced size,weight, power, and cost.
For example, a telecom system consisting of multiple blades, onerunning Linux for the control plane and others for the real-time dataplane can be consolidated onto a single computer, running Linux in avirtual machine alongside the native real-time data plane applications.
In automotive infotainment, the hybrid-visor can be used to combinea rear-seat office experience (e.g. running Windows with Internetbrowsing and Office applications) with the traditional front seatreal-time 'head-unit' radio and navigation functions that requireinstant-on access and bullet-proof reliability.
In the military and intelligence sector, a hybrid-visor can be usedto combine computers and networks managing sensitive information atmultiple security levels onto a single PC.
In this case, native applications are required to secure the sharedHMI devices (screen, keyboard, mouse) as well as to provide a trustedcut-and-paste function between the security domains. Table 1 below provides a partiallist ofapplications and a description of their constituent guest and nativecomponents.
|Table1: Applications of the Hybrid-visor|
Multicore microprocessors are now standard in PCs and servers.According to recent surveys, single-chip multicore designs now accountfor approximately 10% of all embedded designs, with this number slowlybut steadily increasing.
Desktop hypervisors have already started to take advantage ofmultiple cores, allowing both standard and symmetric multiprocessing(SMP)-enabled guest operating systems to execute on multiple coressimultaneously.
Multicore architectures can improve the usability of hypervisors.For example, on a dual-core system, a separate virtual machine can bebound to each core, enabling a guaranteed quality of service for eachguest.
In a hybrid-visor system, real-time applications can be assuredoptimal response time by being bound to a core independently of thecore(s) running guest operating environments. The proliferation ofmulticore devices is likely to increase the proliferation ofhypervisors: symbiotic growth for two disruptive technologies.
David Kleidermacher is ChiefTechnology Officer, Green Hills Software