Improving CMOS image sensor performance with combined pixels -

Improving CMOS image sensor performance with combined pixels

CMOS image sensors have long offered intrinsic advantages in terms of power, system integration, form factor, and overall system cost. Since the adoption of CMOS technology has been hampered historically by image quality issues, camera designers have primarily relied on CCD technology to provide the image quality required for consumer and professional imaging applications.

Now, design engineers have an innovative, better-performing new CMOS image sensor technology available for devices that incorporate imaging technology, such as camera phones, web cameras and digital still cameras.

This option, now available to electronics engineers, is the use of CMOS image sensors that incorporate Kodak PIXELUX technology.
This proprietary technology leverages three key design elements: a four-transistor pixel architecture; use of a pinned photodiode; and a shared pixel design. These combine to enhance image quality through improved photosensitivity and reduced noise, as well as to offer novel charge-binning modes of operation that provide further improvements in image quality with reduced resolution.

Today, the predominant architecture used in the design of CMOS image sensors is based on a three-transistor (3T) pixel design. A typical 3T pixel consists of a photodiode (PD), Reset Gate (RG), Row Select (RS), and source follower, as shown in Figure 1. To read the charge at a given pixel, the pixel is first reset to the voltage level VDD using the Reset Gate RG. This pixel is then left to integrate light, decreasing the voltage across the photodiode as photons are converted to charge, with the final voltage level stored on the common column line. Next, the pixel is reset a second time. This time, the reset voltage is measured and also stored on the column line. The column circuit then samples (the signal and then the reset value) and subtracts these two values to obtain the final pixel value. The pixel measurement, in turn, is the difference between the voltage levels at reset and after light integration.

Figure 1: A typical 3T pixel

While this subtraction would appear to provide an accurate measure of the signal integrated by the pixel, this is not always the case for the 3T architecture. This is because each time the photodiode is reset, it resets to a slightly different voltage. Since the reset level before the integration and the reset after the integration are slightly different, there is an error introduced into the subtraction. This error is a random noise source, and is sometimes referred to as kTC noise, in reference to the equation that determines its magnitude. In addition, since the reset level is measured after the pixel has been integrated, the reset and pixel values are not truly correlated. In addition to kTC noise, several other noise sources are intrinsic in 3T pixels:

  • The sense node where the photodiode and reset gate meet on a 3T pixel typically incurs a high dark current due to process-induced damage and hence produces unwanted noise to the image.
  • The output response of a 3T pixel is non-linear because the photodiode’s capacitance is voltage dependent. As the photodiode fills up and the signal increases, the charge-to-voltage conversion factor gets lower. This can lead to objectionable color artifacts in the image.
  • Residual charge on the photodiode brings about image lag in fast-changing dark to light settings which can cause ghost images.

To address these concerns and improve the overall image quality available from small-pixel CMOS devices, Kodak has developed a new pixel architecture that incorporates both design and manufacturing improvements to the standard 3T CMOS pixel. These improvements – incorporation of a four-transistor architecture, use of a pinned photodiode, and a design that shares readout circuitry across multiple pixels – are collectively known as PIXELUX technology.

As shown in Figure 2, the 4-transistor (4T) design adds an additional transistor (the Transfer Gate TG) and a floating diffusion (FD) to the standard 3T CMOS pixel. Here, a pixel is reset when the Reset Gate and Transfer Gate are turned on simultaneously, setting both the floating diffusion and the photodiode to the VDD voltage level. Next, the transfer gate is turned off (disconnecting the photodiode and floating diffusion) and the photodiode is left to integrate light.

Figure 2: 4T Architecture

After integration, the signal measurement occurs. First, the reset transistor is turned on and off to reset the floating diffusion. Immediately after this, the reset level is sampled from the floating diffusion and stored on the column circuit. Next, the Transfer Gate is turned on and off which allows charge on the photodiode to transfer to the floating diffusion (FD). Once charge transfer is complete, this charge (the photodiode signal level plus the floating diffusion reset level) is measured and stored on the column circuit as well.

These two stored voltages are then differenced to determine the photodiode signal level. This design allows for true Correlated Double Sampling (CDS) operation to occur, as the reset level used to determine the absolute pixel level is now measured before the signal level and the same reset level is referenced throughout the measurement. By mimicking the operation of a CCD, this 4T design significantly improves on the performance of the standard 3T architecture, reducing both read noise and image lag.

In addition to the 4T design, PIXELUX technology also incorporates use of a pinned photodiode. Through a patented ion implantation process, a potential barrier is created that covers up damage at the surface of the photodiode and buffers the vital signal electrons from that area. This suppresses the dark current and lowers the noise in the image. Pinning the surface potential enables readout of all electrons from the photodiode and helps to eliminate the pixel’s “memory” of previous integrations, reducing image lag.

PIXELUX technology also incorporates a novel architecture that utilizes a common read-out circuit for multiple pixels. An example of this design, demonstrating sharing across four vertical pixels (4T4S), is shown in Figure 3.

Figure 3: 4T Shared Pixel Architecture

Here, each pixel has a unique Transfer Gate TG but shares a common readout circuit. As such, each individual pixel can be read out separately by activating TG1, then TG2, etc. Or multiple pixels can be combined in a single read operation by activating more than one transfer gate simultaneously (in the example above, TG1 and TG3 to bin red pixels, TG2 and TG4 for green pixels).


Two specifications determine the sensitivity of an imaging device. First is the sensor’s capability to convert light into signal, usually expressed as its quantum efficiency. The second is the sensor’s noise floor, which limits the ability to capture a useful image in low light conditions.

The PIXELUX architecture increases the quantum efficiency because of an increased fill factor—the portion of the pixel devoted to capturing light. The presence of an additional transistor relative to a 3T design appears to reduce the overall fill factor of the pixel, an issue that is particularly noticeable for small-pixel devices.

However, by sharing common readout elements across multiple pixels, the overall fill-factor of the pixel can be increased in a 4T4S design, providing improved performance.

As an example, consider the 4T4S design shown in Figure 3. Here, a total of seven transistors are shared across four different pixels, resulting in the equivalent of 1.75 transistors being allocated for each pixel. In this shared design, therefore, the fill factor of the pixel is actually higher than what is possible with the 3T design, while still leveraging the image quality improvements associated with the 4T architecture. The fill factor is even more improved when compared to a standard 4T un-shared design.

Sensitivity is also improved by reducing noise. The pinned photodiode lowers the noise associated with the dark current of the photodiode, and the 4T architecture allows for true correlated double sampling to eliminate kTC noise. These factors combine to improve the overall Signal-to-Noise Ratio (SNR) of the PIXELUX pixel relative to the standard 3T pixel, as shown in Figure 4. All these considerations: high quantum efficiency, low dark current, and low read noise; translate into higher image quality, especially in poorly lighted environments.

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In addition to improvements in fill-factor, the use of a shared pixel design directly supports the charge binning of multiple pixels, leading to a significant improvement in sensitivity when the sensor is operated at reduced resolutions. Unlike pixel averaging, the signal from multiple pixels in binning mode can be combined in the charge domain before read noise factors are introduced to the signal. Two binning modes are described below.

Same-Color PIXELUX Binning
In same-color PIXELUX binning, pixels of a single color are combined in the charge domain and then digitally averaged across rows to generate a reduced resolution color image that offers increased frame rate and sensitivity. This is illustrated in Figure 5 for a 4 x 4 pixel array (four instances of a 4T4S grouping).

Figure 5: Same color PIXELUX binning

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In this example, pixels R1 and R2, G1 and G2, etc., are binned vertically and then horizontally digitally averaged to produce an image with a quarter of the resolution of the original array. Because the summed charge from two pixels is being measured in a single read operation, the overall signal-to-noise ratio of the resulting image is increased as shown in Figure 6. Here, the blue line shows the 4T SNR curve from Figure 4, while the dotted green line represents the SNR curve associated with a standard 4-pixel averaging configuration (first, reading the entire pixel array, and then performing a 2×2 average digitally). The solid green line shows the SNR curve from a sensor operating in PIXELUX mode with the same-color binning.

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Figure 6: SNR increase with PIXELUX binning modes

Continued on Page 3: Image examples

This increase in sensitivity can also be seen in the images shown in Figure 7. The left column shows an image captured using same-color binning mode of the Kodak KAC-3100 image sensor, a 3.1 megapixel sensor with 2.7 micron pixels. The center panel shows a second image captured with binning turned “off”, and demonstrates the native sensitivity of the pixel array. Since all other capture conditions were held constant, this image is now underexposed relative to the left column. The right column again shows an image with binning turned “off”, but now with the electronic gain of the capture system increased to match the exposure of the binned image. The difference in observed visual noise between the right and left columns in this Figure, therefore, arises directly from the increased sensitivity available from same-color PIXELUX binning.

In addition to this sensitivity increase, binning also increases the effective frame rate of the sensor when it is operated in this mode. Since two pixels are measured in a single read operation, the total number of read cycles required to clear the sensor is reduced in half – thus effectively doubling the frame rate relative to operation in non-binned mode. When the frame rate is limited by a lack of light, same-color binning increases the frame rate by decreasing the required exposure time.

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Figure 7: Sensitivity improvements from Same Color PIXELUX binning

The combination of enhanced sensitivity and increased frame rate makes same-color PIXELUX binning an attractive mode for video capture. With a megapixel sensor, the native resolution of the sensor needs to be reduced to support standard video formats; Same-color PIXELUX binning provides a path to reducing the resolution while increasing the sensitivity and frame-rate of the device, without the objectionable aliasing artifacts caused by line thinning.

All-Color PIXELUX Binning

All-color PIXELUX binning extends this concept by combining all of the pixels within a four-pixel shared cluster, as shown in Figure 8. This mode provides high frame rates with very high sensitivity (see Figure 6) for use under extreme low-light conditions. The resulting monochrome image (at 1/16 the resolution of the sensor) utilizes the charge captured by all pixels in the array (no subsampling is used).

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Figure 8: All-Color PIXELUX binning

This operating mode is ideally suited for auto-focus applications, a highly iterative process that requires fast capture at very high frame rates, making it increasingly difficult to detect edges in low-light settings. This mode is also ideal for electronic viewfinder applications as it allows the user to frame the picture in video mode – even under very low light conditions – prior to taking a full resolution snapshot with a flash.


By incorporating new design elements, including the use of a four-transistor architecture, pinned photodiode, and shared pixel architecture, PIXELUX technology enables significant improvements in the image quality available from CMOS image sensors. All in all, this technology offers significant benefits relative to traditional CMOS pixel architectures, enabling innovative products that deliver a competitive advantage in today’s demanding imaging marketplace.

About the author
Failop Chu is is an applications engineer in Kodak's Image Sensor Solutions Group. For more information, contact or visit .

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