Many IoT applications – including connected cars, factory automation, smart city, connected health, and wearables – require nonvolatile memory to store data and code. Traditionally, embedded applications have used external Flash memory for this purpose.
However, as modern semiconductor technology faces challenges in scaling and cost as it moves to smaller geometries, it has become increasingly difficult to embed Flash memory within the host SoC. Therefore, future MCU or SoC designs are targeting system-in-package (SiP) or the use of external Flash. This trend does not address the needs of IoT applications like wearables because of their small form factor, strict cost constraints, and low-power related requirements.
To address these issues, Flash memory manufacturers are developing architectures that optimize size and power consumption. At the same time, they are introducing important new capabilities that support greater endurance, reliability, security, and safety.
Legacy and present-generation wearables require low-density NOR flash solutions to store code, but they need higher densities will grow as applications become more complex and they need to log more data. New cell architectures enable greater memory capacity. For example, MirrorBit technology can store two bits per cell and supports products up to 4 Gb of density. This increase in density allows for between a 20% to 30% smaller die size compared to the traditional floating gate NOR Flash architectures. This smaller die size also increases packaging flexibility for external memory. A smaller die size is a suitable option for SiP solutions or an external nonvolatile memory with wafer-level chip scale packaging (WLCSP).
To support access speed to the larger memory array, a high-speed interface is required. The Semper NOR Flash from Cypress, for example, has a Quad SPI protocol running at 102 MB/s and xSPI protocol running at 400 MB/s speed. High-speed interfaces are necessary for high-performance IoT applications as well as for applications that require instant-ON capability and Execute-in-Place (XiP) from NOR flash.
Figure 1. Technologies like MirrorBit are being developed by memories manufacturers to improve memory density. (Source: Cypress)
In addition to greater memory size, new architectures are more flexible as well. Code, data, and data-logging each have different storage requirements. With a flexible sector architecture that allows developers to configure the sector size and provide a continuous addressing scheme, it becomes possible to segment memory in a manner that best matches the code or data being stored there.
As IoT devices continue to expand into a greater variety of applications and operating environments, the requirements for safety and security become stricter as well. The memory that stores code needs to allow the system to boot from memory, log sensor data, and perform XiP functions. These functions are not easy to implement with a traditional NOR flash architecture.
Consider a typical IoT application with an applications processor that has internal RAM connected to external NOR flash. These applications often store application code and data in the NOR flash memory and download everything from the NOR flash to the internal RAM at power-up. This use case is called “Store and Download” (SnD), which is shown in Figure 2. The internal RAM density of the application processors limits IoT system performance improvements such as faster over-the-air updates, improved display performance, increased networking throughput, improved audio performance, sensor fusion over SPI/UART, and arithmetic operations. Such improvements require a BOM change because of the limited internal RAM density.
Figure 2. Store and Download (SnD) use case. (Source: Cypress)
Figure 3 shows how the processor can copy data from the NOR Flash and execute code with XiP directly from the NOR Flash upon power-up. With this approach, the processor has more internal RAM available for application improvement. Hence, using XiP enabled by NOR Flash allows IoT applications to be improved without any performance impact.
Figure 3. Execute in Place (XiP) use case. (Source: Cypress)
Typically, NOR flash is used for random fast read purposes only because of endurance and reliability issues. All flash memory is subject to physical degradation at high numbers of program/erase cycles that can eventually lead to device failure. Some IoT applications need high endurance and high retention in flash devices; lower data retention or endurance may affect the system functionality.
Memory manufacturers are working on new architectures that improve endurance so that applications can now perform data logging with NOR flash. For example, the EnduraFlex architecture in Cypress’ Semper Flash optimizes system design by enabling a Flash device to be divided into multiple partitions. Each partition can be independently configured for either high endurance or long retention. For frequent data writes, a partition can be configured to deliver up to 2.56 million program/erase cycles as compared to 100,000 cycles in a typical NOR flash device. Similarly, data retention can be improved as well, up to 25 years.
Safety and Security
Code and sensitive user data (such as with a medical wearable) must be secured, both in terms of safety (i.e., reliable operation by preventing corruption of data) and security (i.e., protecting data from hackers). To achieve this, memories are becoming smarter and integrating processors like the embedded Arm Cortex-M0 CPU to handle complex safety- and security-related embedded algorithms on chip (see Figure 4). This enhances reliability while helping to improve device performance, safety, and security.
Figure 4. Today’s NOR Flash memories for wearables provide greater capacity as well as many security and safety features. Shown here is the Semper NOR Flash memory architecture from Cypress. (Source: Cypress)
With an integrated processor, NOR Flash is also able to support a variety of features and diagnostics that provide end-to-end data integrity and protection. NOR Flash supports traditional Advanced Sector Protection (ASP) schemes as well as a 1 KB One-Time Programmable (OTP) region, but these features are not sufficient for certain IoT or wearable applications. Advanced NOR Flash enables additional end-to-end security solutions, including cloud-to-flash security, secure firmware-over-the-air (FOTA) updates, and secure write protection.
Power efficiency is another important consideration for wearables. Wearable devices tend to use the active power of NOR flash devices for a very short time. At all other times, the NOR flash device stays in standby or deep power-down mode. Also, the majority of wearable devices operate on battery power. This requires a NOR flash device with a low standby- and deep-power-down current. Today’s NOR Flash memories can support low standby current on the order 6.5 µA and deep-power-down current on the order of 1 µA.
Even though wearable devices tend to operate in environments at room temperature, some IoT applications need to be able run reliably at extreme temperatures. For these applications, industrial memories are available that can handle ambient temperatures from -55°C to +125°C.
Wearable devices are an important part of future IoT market growth, with requirements ranging from form factor, power, and cost, to safety and security. With advances in NOR Flash technology such as an integrated processor, these memories can provide the greater density, lower power, higher security, and greater performance in the
Pritesh Mandaliya is an applications manager in the Cypress Semiconductor Memory Products Division focusing on NOR Flash product development. Pritesh has more than eight years of experience defining Sync SRAM and NOR Flash memory products. He is currently engaged in next-generation NOR Flash product definition, while also supporting customers, worldwide sales and FAE teams with solutions, technical articles, training, and demos.