Impulse Accelerated Technologies has just made available its Impulse C and CoDeveloper revision 3.7, which compiles C algorithms to Altera’s Quartus revision 12 Qsys software. It is designed tol allow embedded software developers to more easily compile C based algorithms for fast integration into Altera Stratix and Cyclone FPGAs.
When software developers use FPGAs to accelerate compute-bound microprocessor algorithms, they run into a number of problems. One is that because they are not familiar with VHDL, despite the fact that it was based on the Ada embedded programming language. Second, they do not fully understand the nature of hardware resources on FPGA nor those on an FPGA based development board. Also, most developers find it hard to partition code between running on FPGA hardware and running, often over PCIe, on the host processor.
The new Impulse C 3.7 bridges these gaps by adding an interface between C algorithms and hardware resources that readily integrates within Qsys and Quartus. This lets a software developer refactor microprocessor oriented C into coarse-grained logic, that is easily machine-parallelized into multiple streaming processes.
These processes run in FPGA hardware or are partitioned to run native on the host processor, or on available processor cores from Altera. The cross-compiled code remains fully ANSI C compatible so it can be simulated within standard tools such as MS Visual Studio.
For cycle-accurate HDL verification, Impulse C also provides a direct export of a test bench to Mentor ModelSim or Aldec Active HDL. Software developers can work within a C development tool such as Visual Studio to offload the microprocessor code via parallelized optimization to FPGA.
Developers interested in trying out the new capabilities should go to www.ImpulseC.com and request an evaluation. Impulse also provides design services and free design consultations.