MADISON, Wis. — In a microprocessor and microcontroller IP core market that is dominated by ARM's massive IP portfolio, the relevance — even survival — of a competing 32-bit processor IP company is no cakewalk.
Cortus, a 32-bit microprocessor IP vendor based in Montpelier, France, has successfully battled ARM Cortex M0 in the deeply embedded market for nine years. Moreover, Cortus believes its “minimalist” approach is the key to a strong foothold in the emerging market of connected devices.
On Tuesday, Cortus is rolling out a new family of products based on its second-generation (v2) instruction set. The company says its increased code density will meet the power and size requirements of new connected devices.
Responding to continuing demands for less power drain in system-on-chip (SoC) designs, Cortus has developed an instruction set aimed at reducing the size of a system's instruction memory. The APS23, the first product to use the v2 instruction set, is aimed at low-power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Low Energy.
Cortus president and CEO Michael Chapman told EE Times that it has focused on reducing the size of the instruction memory, which he called “the largest single component in a system.” With the v2 instruction set, Chapman claimed an average 16% improvement in code density over the company's v1-based cores.
Simultaneously, Cortus is announcing the APS25 IP core, the second in a family of products based on the v2 instruction set. The core is designed for embedded systems that require greater computational performance and system complexity by supporting dual- and multi-core systems and improved code density.
Co-processor interface and security
Kevin Krewell, principal analyst at Tirias Research, said Cortus has a fighting chance against ARM because of the “options and flexibility” Cortus provides its licensees.
Cortus IPs are uniquely different from those of its big rival, ARM, because they offer “a co-processor interface and security,” he said. “ARM, in contrast, has thus far resisted offering a co-processor interface while keeping a very tight control over its instruction set.”
According to Cortus, the company's co-processor interface allows its licensees to add and design specific algorithms while giving them full access to CPU registers. The licensees can do so with no knowledge of the CPU internals.
The best example of this distinction lies in security implementation. Certicom, a subsidiary of BlackBerry, used Cortus's extendible instruction set for a Galois field multiple in elliptic curve encryption/decryption. Cortus IP allowed Certicom to couple its security tightly with a CPU. Krewell said this is a key differentiator for Cortus in the emerging Internet of Things (IoT), where “the need for security is paramount.”
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