In-memory compute enables more efficient edge processing -

In-memory compute enables more efficient edge processing

New in-memory computing technology eliminates need to move large amounts of data around chip, to help addressing latency for time-critical applications, and power efficiency for IoT devices.

sureCore has announced a new technology for in-memory compute capability, to enable more power efficient edge-based data processing for IoT devices.

The company said its new CompuRAM in-memory computing technology eliminates the need to move large amounts of data around within a chip, which can help edge computing in terms of both addressing latency for time-critical applications, and power efficiency for IoT devices. In the same way that on-chip memory can be faster and more power efficient than transporting data back and forth to off-chip memory, integrating memory and compute capability can improve on this and provide more power saving benefits.

sureCore said its in-memory compute technology achieves this integration by embedding arithmetic capability deep within the memory array in a way that is compatible with its existing silicon-proven, low-power memory design.

Hence sureCore’s CTO, Tony Stansfield, explained that by integrating arithmetic operations within the memory, they’d be ready to deliver a solution for edge AI when that starts becoming more mainstream.

Tony Stansfield - sureCore CTO
Tony Stansfield

Stansfield told, “There are two basic ways that in-memory compute can reduce power. The first is by reducing the need to move data around on-chip – as stated, this is similar to reducing power by keeping data in on-chip memory rather than off-chip memory; the shorter the distance that data needs to move then the less energy it requires to move it. The second is by using power-efficient ways to implement the necessary compute functionality.”

He added, “The first of these is common to all approaches to in-memory computation, whereas the second is very implementation specific. The sureCore path to power-efficient computation builds on our existing ways to implementing low-power SRAM:

  • We save SRAM power by achieving precise control of capacitance, and precise control of voltage swings on that capacitance, using voltage swings that are no greater than needed for reliable data transfer. This makes data transfer effectively an analog issue. Applying the same ideas to our compute logic means that part of the computation happens in the analogue domain, using reduced-swing signals.
  • We use hierarchical techniques in our SRAMs, so that only those sections of the memory that are required in order to access a particular address are activated. For computation, we can activate multiple sections simultaneously, and then combine their outputs as they propagate through the hierarchy. This gives us high bandwidth when processing large amounts of data, but with low data transfer power as the tracks are local to the memory system.”

How in-memory compute impacts edge AI

In IoT devices where sufficient edge processing resources are not available, then sensor data frequently gets sent to a server for processing, which both creates a need for connectivity overheads, and can add unavoidable latency. For time critical applications, this latency can be an issue, which is the main reason why there is a drive to do more computation within the device itself. On top of that, power is also a significant design constraint in IoT devices, and so any extra AI-related computation needs to be carried out in a power-efficient way.

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