Increase your boot options with Managed NAND -

Increase your boot options with Managed NAND

A standard interface combines with an on-chip controller to handle the wear-leveling and write/erase timing, as well as the memory management functions of your NAND memory.

Nonvolatile memory has many functions in a processor-based system, but one of the most critical is providing the initial firmware that the processor must use in its system initialization (boot) process. Both NAND flash, with its interface challenges, and NOR flash, with its relatively low density, are unsatisfactory for use as single, nonvolatile, bootable system memory. Managed NAND offers a third alternative, once the challenge of making it bootable has been solved.

Portable devices, such as personal media players (PMPs) and portable navigation devices (PNDs), have at least two requirements for nonvolatile semiconductor memory. One need, common to all processor-based systems, is nonvolatile program storage. For many systems, only the power-up initialization or boot programs need to reside in semiconductor memory. PMPs and PNDs, however, typically need their entire software package, including applications and operating systems, in semiconductor memory. This requires at least moderate memory capacity, from tens to hundreds of megabytes. In all cases, the memory must be compatible with the processor's boot process.

Second, these systems must have user data storage. In the case of PMPs, the data would be music and video files. For PNDs, the data include maps, location markers, and movement histories. What these data types all have in common is large size. User storage capacity of hundreds of megabytes to gigabytes is quickly becoming a consumer expectation. Unlike program storage, the data memory can be block-oriented rather than pure random access.

The nonvolatile memory of choice in today's devices is flash, which stores its data as a charge imposed on a floating gate in a CMOS transistor, as shown in Figure 1. The presence of the charge determines the transistor's state, hence the memory cell's data value. Because the gate is floating, with no direct connection to any other circuits, any charge placed on the gate remains indefinitely unless deliberately removed.

To charge or discharge the floating gate, the memory cell must impose a high-voltage signal on the transistor's other gate. Electrons then tunnel to or from the floating gate. This high voltage stresses the insulators and crystalline structures around the floating gate and can eventually damage those structures, rendering the memory cell useless. This wear-out mechanism is common to all forms of flash memory.

Another attribute common to all flash memory is the need to erase a cell before writing to it. Because a cell's state may not be known before attempting to store data into it, the control logic on flash devices first puts the cell into a known (erased) state before configuring it with data. Thus, every time a cell is written to, it suffers some wear-out damage.

Two distinct flash memory architectures have arisen: NOR and NAND. NOR, as shown in Figure 2, has an SRAM-like structure. Each individual bit in the memory connects to the word and bit lines of the device's internal addressing circuitry and the output level is normally high. If a memory cell has been programmed, activating it with the proper word line causes it to pull the bit line low, as with wired-NOR logic.

The individual bit connections give NOR flash a relatively simple RAM-like external interface and high read speed. Erasing or writing to the memory, especially in large blocks, takes extra time, however. Each bit in the block must be individually erased to prepare the block for writing, which can add up to a significant amount of time if the block is large.

NAND flash connects memory bits in series, as shown in Figure 3.

The transistors in the series are normally “on,” keeping the bit line low. Activating a programmed transistor with the word line will make it turn off, breaking the series connection and allowing the bit line to go high. This configuration offers slower read speeds due to the impedance of the series connections. Eliminating most of the bit line connections, however, makes NAND cells more compact than NOR cells, allowing NAND memories to achieve higher densities. Another density boost for NAND has appeared in the form of a multi-level cell (MLC) topology. In this approach, each bit location stores one of four voltage levels on the floating gate, allowing the cell to encode two bits of data instead of one, as shown in Figure 4.

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The price for this increased density is a more complex interface. Used primarily for solid-state storage and file systems, NAND flash uses a block-oriented storage structure rather than byte-oriented addressing. NAND also uses a multiplexed address and data interface to reduce its I/O pin count. As a result, NAND flash doesn't simply connect to a processor's external bus like SRAM. Often, it requires a specialized interface.

Regardless of the architecture, however, flash-memory devices all need some management to maximize their use. These functions include bad bit/block identification, error detection/correction, and wear-leveling. Wear-leveling is especially important for maximizing the usable lifetime of a flash device. If designers allow write/erase activity to be concentrated in one section of memory, that section will wear out, while the rest of the memory has plenty of remaining life. Wear-leveling algorithms shift that activity around to prevent any one address from wearing out quickly.

Because the wear-out mechanism is a function of how long the cell is exposed to high voltages, flash vendors have developed complex erase/write timing algorithms to ensure reliable programming and erasure with minimum exposure. These algorithms, along with all the other memory-management functions, are unique to each vendor. As a result, developers typically implement flash-memory management in software.

Despite these complexities, flash memory has earned a place in PMP/PND designs. These designs require high-capacity data storage for detailed large-area maps and multimedia files along with bootable program storage, both of which must be nonvolatile. In addition, memory for these products must be low power and low cost to meet the market demands for long battery life and reasonable pricing.

Unfortunately, no one type of flash meets all of those needs well. The density of NOR is too low, making the cost per byte too high to serve as data storage. NAND's interface is complex, so it can't typically serve as bootable program storage because the processor needs intelligence (in the form of software) to access the memory. The need for memory management further complicates the use of NAND; MLC NAND is even more complex.

As a result of these limitations, most PMP/PND designs use both types of flash–NOR for bootable program storage and NAND for mass storage. This practice adds extra ICs, hence extra cost, to the design. Furthermore, it requires some processor overhead for handling the NAND interface and memory management functions.

While raw flash memories don't meet all the design's requirements, there's an option that will–Managed NAND. Managed NAND devices include an on-chip controller that handles the vendor-specific algorithms for wear-leveling and write/erase timing, as well as the memory management functions of the NAND memory, as shown in Figure 5. This eliminates the software overhead associated with NAND and allows Managed NAND devices to offer a standard, vendor-agnostic interface to the system processor. Two interface standards are available: the Multimedia Memory Card (MMC) and the Secure Digital (SD) card interfaces.

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The challenge with using Managed NAND in a PMP/PND design is making it bootable. Because the standard interfaces aren't SRAM-like, processors need some kind of adaptor to connect to them for memory access. Some processors have embedded SD/MMC interfaces, but those that have them don't have them located at the boot address. A purely software-based interface can't be used for boot operations because the system must be able to access the memory to load the software. Any external hardware-based interface would need to be configured before the processor can boot as well.

Booting from Managed NAND
The solution to boot from Managed NAND thus needs two parts: a hardware component and a software component. The hardware component bridges the processor and Managed NAND to make the memory look like simple ROM to the processor. The software component is an initial program loader (IPL) routine that performs minimal CPU initialization and transfers the boot-loader code from the Managed NAND to the processor. Working together, these two components can take the system past the initial chicken-and-egg situation of needing software to load the software, allowing the Managed NAND to serve both as program and data storage.

One vendor has implemented a boot interface to Managed NAND using an SDIO/MMC host controller. This device offers configurable interfaces, making it adaptable for use with most processor families, as well as with SD, SDHC, and MMC Managed NAND memories. For processors already possessing these interfaces, the host controller expands its capacity and offers a boot capability. The configurable interfaces also let the device connect with a CE-ATA hard disk drive using the same interface as for the memory card. With on-chip RAM available, the controller can hold the IPL code for the processor to access during the boot process.

This implementation can perform an entire boot sequence under both Linux and Windows CE operating systems using a Marvell PXA270 processor, or a TI OMAP platform. It's been tested with various SD, SDHC (high capacity), and MMC Managed NAND devices and has built-in autodetection of the memory interface to perform the proper device initialization sequence.

Booting from Managed NAND imposes both hardware and software requirements on a design. The hardware requirements, shown in Figure 6, include a connection to the boot chip-select line coming from the processor as well as control of the reset line. The reset line control lets the host controller prevent the CPU from operating until the Managed NAND boot interface is ready. The boot chip-select line's memory interface configuration is also reconfigured after power-up to support the use of a READY signal to gate access to memory.

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One software requirement is the development of an IPL program specific to the processor being used. The RAM capacity of the QuickLogic SDIO/MMC host controller, 2 kbytes, dictates that the IPL program be limited to 512 instructions, assuming a 32-bit processor. The IPL code thus must be optimized for the CPU and architecture it's supporting. While 512 instructions is a small program space, it's an adequate size, especially if the processor also has on-chip RAM available for holding stacks and variables. The processor's on-chip RAM is also useful for storing and running the boot-loader program later in the process.

The IPL code isn't the only software that must be adapted to the processor and architecture. The system's boot-loader code must be adapted so that the processor executes the code out of its internal RAM rather than external ROM. It must also support reading the code through the Managed NAND memory interface. Similarly, the operating system will require drivers to be able to use the host controller to its full capability once the system has booted.

Three-stage boot process
With both the software and hardware elements in place, the boot process follows a three-step operation.

At power-up, the host controller keeps the processor in a reset state while it downloads the IPL code from Managed NAND into its internal RAM. It then maps its internal RAM to serve as SRAM to the processor under control of the processor's boot address chip select and releases the CPU from its reset state.

Once released, the CPU begins executing the IPL from the host controller's RAM. The IPL code uses the controller to load the boot-loader code into the processor's internal SRAM. The IPL then jumps to that SRAM address to begin executing the boot loader.

The boot loader initializes system SDRAM and then loads the operating system from the Managed NAND into system SDRAM. Once the operating system is loaded, program execution jumps to the operating system, concluding the boot process.

After the boot process is complete, the remainder of the Managed NAND device–the portion not containing the boot software–can be accessed by the operating system as a storage device within the file system. The amount of Managed NAND required to contain the boot software (the IPL, boot loader, and operating-system image) is relatively small, around 64 Mbytes. The Managed NAND can be partitioned and formatted so that the remaining majority of the device can be accessed as user storage, while the 64-Mbyte boot portion is protected and kept secure by design.

This approach gives PMP/PND designers many benefits. For example, it simplifies board design and saves parts cost. Using Managed NAND for both program and data storage eliminates the need for a separate NOR device. In addition, the interface to Managed NAND uses fewer I/O lines, requiring only six lines versus 16 or more, for a conventional memory interface.

Because the Managed NAND offers standard, vendor-agnostic interfaces, designers have more supply options available to them. They can go with MMC or SD memory devices, both of which have JEDEC-standard pin-outs, and have a wide range of suppliers to choose from. Unlike raw NAND, there's no vendor-specific software needed.

The SDIO/MMC Host Controller can also connect to multiple MMC- and/or SD-based Managed NAND devices simultaneously, as the controller can be customized to include a multiplexing structure for multiple SD devices or can be compatible with a multi-load MMC bus. This lets designers mix and match memory suppliers and densities to minimize bill-of-materials cost while satisfying design requirements. For example, in a PND, design requirements may call for 3Gbytes of storage to accommodate map and point-of-interest data. To satisfy this requirement, a designer would typically choose a 4-Gbyte Managed NAND, but with the SDIO/MMO host controller, the designer can choose a less expensive two-chip approach (2Gbytes + 1Gbyte).

Using Managed NAND also helps future-proof designs as storage demands move above 4 Gbytes. The standard interfaces of Managed NAND hide the complexity of multi-level circuits, allowing designers to double memory capacity simply by changing to the new technology. The configurable nature of the SDIO/MMC host controller also ensures that developers can move to SDHC memories as needed. Such a move would be complicated when using raw NAND flash because the higher density devices use block-oriented addressing rather than the byte-oriented addressing that processors expect. File structures for high-density devices also move, from FAT16 to FAT32, further complicating adoption of high density.

Judd Heape is a principal architect and senior director of systems engineering for QuickLogic Corp. in Sunnyvale, Ca. He has five granted U.S. patents and has authored one worldwide JEDEC standard. Judd holds a degree in electrical engineering from the Georgia Institute of Technology. He can be reached at .

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