Part of the high speed logic family of devices, the 1385DX, with its high sensitivity latched comparator input and auto-synchronizing demultiplexer, enables test and measurement, defense, and aerospace designers to develop high speed data acquisition front ends and to deserialize high speed signals.
The 1385DX features a high-speed sampling clock and high-bandwidth latched comparator input that can be used to sample high-bandwidth analog signals and demultiplex them to a lower data rate for post-processing via a low speed FPGA or ASIC.
The high bandwidth input supports digital signals up to 12.5-Gbits/s, which are latched and deserialized to an eight bit parallel output bus. The 1:8 deserialization, coupled with an on-chip synchronization circuit and adjustable output levels, allow the use of multiple demultiplexers in parallel, with automatic alignment of the parallel output buses of the demultiplexers.
Availability: Shipping in pre-production quantities in an 8×8 mm QFN package or on an evaluation board with SMA connectors. Full production is expected to begin in the first quarter of 2008.
For more information: click here.
Inphi Corp., www.inphi-corp.com