Integrated design flow targets Lyrtech multiprocessing systems - Embedded.com

Integrated design flow targets Lyrtech multiprocessing systems

LONDON — Multiprocessor design software provided, 3L Ltd., and Impulse Accelerated Technologies Inc., developer of the CoDeveloper suite of C-to-FPGA design tools, have produced a design flow that targets multiprocessor systems from signal processing specialist Lyrtech Inc.

By integrating the 3L (Edinvburgh, Scotland) Diamond multiprocessor tool suite and CoDeveloper, the design flow accelerates the creation, debug, verification and implementation of very complex applications that require multiprocessor performance.

The Diamond tool suite helps the designer create tasks that are self-contained blocks of code which communicate with other tasks on DSP, FPGA or GPP fabrics. The low latency inter-processor communications and synchronization between the tasks are automatically created by 3L Diamond.

The joint solution provided by 3L and Impulse (Kirkland, WA) is claimed to provide a level of design abstraction that is unique for DSP+FPGA multiprocessor systems.

The Impulse CoDeveloper tools allow C-language applications to be quickly and efficiently retargeted to FPGA devices. This enables application developers to rapidly exploit the inherent parallel processing features of FPGA technology and accelerate signal processing applications.

When this capability is put together with 3L Diamond, the shared level of abstraction can mask platform level details and offer designer independence from the hardware. And because the application structure is independent of the processors on which the tasks are placed, the designer has greater freedom to explore the design space by simply dragging and dropping different tasks onto different processor targets, at any stage of the design flow.

The joint 3L/ Impulse design flow is targeted in the first instance at Lyrtech's (Quebec City, Canada) SMQ range of DSP-FPGA high performance computing platforms. The SMQ (SignalMaster Quad) features a combination of FPGA and DSP devices designed around two clusters of one Virtex 4 LX FPGA and two TMS320C6416 DSPs.

Each cluster can yield up to 16,000 MIPS/MMACS of DSP processing power and 48 GMACS of FPGA-based DSP processing power. It features Dual LYRIO+ very-high-speed expansion sites, 128-Mbyte external SDRAM per DSP and FPGA, and six 8-Gbps RapidCHANNEL onboard links.

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