PORTLAND, Ore. — Intel revealed its roadmap for the future of technical computing, including customizing its high-end Xeon and Xeon Phi processors, at this week's Supercomputing Conference (SC13), Nov. 17-22 in Denver.
The company promised to start housing memory chips inside the same package with its processors as well as integrating stacked memory dies onto future processors along with integrated high-speed switches and optical fabrics.
“We have the transistor budget to do customized innovation, and secondly we have a design methodology for system-on-chip and an architectural modularity that allows us the ability to work with our customers to customize products at various levels,” said Rajeeb Hazra, Intel's vice president of the technical computing group and general manager of the datacenter group, in an interview with EE Times.
“We are moving forward into workload-optimized architectures at a level of collaboration with our customers that we hadn't done previously.”
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