Intellitech Corporation has announced support for accessing Silicon Instruments SM through the new IEEE 1149.1-2013 JTAG standard. The new IEEE 1149.1-2013 includes structural and procedural description languages to support re-use of on-chip infrastructure IP or what Intellitech calls 'Silicon Instruments'. Examples of Silicon Instruments are: Memory BIST, I/O BIST, Logic BIST, SERDES PRBS, voltage droop monitors and temperature monitors.
The hierarchical extensions to 1149.1 Boundary Scan Description Language (BSDL) allow self-contained Silicon Instrument descriptions to be supplied by the instrument provider in a new 'package' file format. These descriptions can then be instantiated and connected via new capabilities of 1149.1-2013 that use the IEEE 1500 “Standard for Embedded Core Test” standard. Hierarchical documentation called Procedural Description Language (PDL), based on the open source Tcl, allows the Silicon Instrument vendor to describe the necessary steps to operate the instrument via the JTAG Test Access Port. An engineering manager's tutorial on the benefits of 1149.1-2013 can be found on Intellitech's website at 1149.1-2013 tutorial .
Intellitech's BERT-IP for SERDES BIST and DDR-IP for at-speed memory tests are available from Intellitech's Test-IP family of Silicon Instruments for FPGAs. Those instruments, introduced ten years ago, and upgraded with each FPGA generation, can now be operated on with 1149.1-2013 PDL.
Intellitech will be rapidly growing the use of 1149.1-2013 through a free web-based BSDL syntax and semantic checker compliant with the new standard at 1149.1-2013 BSDL Compiler . The freely available NEBULA product for accessing internal JTAG Silicon Instruments using 1149.1-2013 is available at Silicon Instruments . Engineers with a corporate email account can register on the website and download the software.