Interleaved multi-channel technology increases memory bandwidth in video SoCs - Embedded.com

Interleaved multi-channel technology increases memory bandwidth in video SoCs

Munich, Germany – To improve image quality and support higher resolutions, HQHD video requires the adoption of upgraded video protocols, more image resolution enhancement, and scaling up to 120Hz. This is causing a shift towards utilizing matched groups of processors and supporting subsystems that supply the on-chip processing required to achieve HQHD video performance. The transition to subsystems means that SoC architectures must now become hierarchical. Interconnects within the subsystems are needed to support the local data throughput requirements of the subsystems, and a global interconnect is required for subsystem integration onto a single chip and to manage the global data throughput requirements. Increased processing and subsystem integration complexities results in the need to significantly increase external memory access bandwidth, which is now the primary design challenge for HQHD video SoCs.

SonicsSX is built on the architecture of previous SMART Interconnect solutions. It contains all the advanced fabric features and data flow services, such as universal IP core connectivity, non-blocking multithreaded data flow, and power, security and system error management. To address increased processing for HQHD, SonicsSX offers higher operating clock frequencies and adds native support for 2D data transactions and an expanded data bus to 256 bits. This allows the interconnect data bandwidths to increase from the 2 to 4 gigabytes per second required for high definition video, to up to 16 gigabytes per second for HQHD video.

To improve global shared memory access bandwidth, SonicsSX adds network-on-a-chip capabilities and also contains IMT, which enables SoC developers to transition their architectures from single to multiple DRAM channels, while avoiding the complexities associated with multichannel memory management. IMT utilizes innovative memory interleaving methodology as foundation for managing up to eight external DRAM channels. User-controlled interleaving addresses the key challenge associated with adopting multi-channel architectures, ensuring that the memory traffic is divided evenly among the channels.

SonicsSX is also compatible with the practical Globally Asynchronous Locally Synchronous (GALS) approach that is part of the SMART Interconnect solution. Practical GALS enable SoC developers to extend the capabilities of SonicsSX to include voltage and domain isolation on an IP core or subsystem basis, which further facilitates low power and higher performance. Practical GALS do not disturb SoC design flows, which is typically the case when implementing asynchronous functionality.

SonicsSX with IMT SystemC models are available for advanced architecture modeling. As a member of the SMART Interconnect family, advanced RTL configuration and automation through SonicsStudio enables SoC developers to complete data flow analysis for SonicsSX with IMT during the architecture phase of a product development cycle. This allows SoC developers to realize predictable high performance data flows, including those related to the multichannel memory subsystem, before the hardware and software development phases begin.

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