IoT and wearable devices mean rethinking memory design - Embedded.com

IoT and wearable devices mean rethinking memory design

Wrist radios have been staples in comic books and science fiction for decades, but it has been far easier for writers to conjure up the vision than for engineers to realize the technology — until now. If smartphones are now the ubiquitous embodiment of Star Trek's ‘communicator’, wearables like smart watches, fitness bands, or even rings that turn your finger in a gesture controller, finally bring the latest gadgetry technology to the masses.

Yet wearables aren't merely an evolutionary change to existing mobile devices. Instead the physical dimensions and electrical requirements of wearables are so vastly different than smartphones that they constitute an entirely new hardware category. The disparity in physical size, battery capacity, and usage environment, where things like water and shock resistance are much more important, mean wearables bring a new set of design requirements and constraints. Developers can't just scale existing smartphone designs and expect to have a usable smart watch.

For example, compare two category leading products, the Pebble Smartwatch and the iPhone 5S, for stark contrast in packaging density. The former's case is a mere 43 x 34 mm or about one-fifth the surface area of an iPhone with its 4-inch screen. Within that 10-mm-thick package, Pebble's designers had to pack a 2.3-inch LED display and a single circuit board with memory, SoC controller, various sensors, Bluetooth chip, and battery. All of this on a double-sided circuit board where real estate for components and interconnect is at a premium and where buyers want the slimmest possible device profile.

The demands on wearable designs don't stop with the packaging. Due to limited space for batteries, products must be extremely power-efficient in both active and standby modes, yet start up instantaneously, support Bluetooth communications, and seamlessly run applications that engage the user. No one will buy a smart watch just to tell the time.

Mitigating the design difficulty is the fact that unlike in the comic books, no one expects a smart watch, connected glasses, or fitness band to replace a smart phone. Instead, smart phones are evolving into multipurpose hubs to which a growing constellation of wearable devices connect. This means most wearables don't require high-capacity, persistent storage or fast multicore processors. Add up the capacity, size, and power requirements, and wearables are an ideal platform for NOR flash memory.

NOR flash is the perfect fit for wearables
In the days before smartphones capable of storing a season's worth of TV shows or an entire music library – that is, when mobile phones were just phones — NOR flash was the preferred persistent storage medium. Unlike NAND, which stores multiple bits in series, trading off random access for density and write speed, NOR behaves more like traditional DRAM, in which memory cells can be read and written individually instead of an entire block at a time.

This means NOR can be used for application code that can be executed in place without first being copied to a separate RAM cache. Random access also means NOR flash is capable of high-speed read throughput of up to 20 MB/s for serial (SPI) and 250 MB/s for parallel NOR designs.

The tangible benefits of choosing NOR flash over NAND in wearables are compelling. NOR flash’s direct code execution greatly reduces boot time, meaning devices start up in an instant. Likewise, eliminating RAM needed for code execution means standby power consumption is much lower, yielding longer life when using the tiny batteries that are required in wearables packaging.

Since wearables are generally tethered to another device through which they regularly connect to Internet services and databases, they don't need to store much local data. Even a day's worth of health and fitness measurements is minuscule relative to the size of audio and video files. With physical space in wearables at a premium, NOR flash capacity and die size is much better aligned to application needs than NAND.

This next point may seem counter-intuitive since NAND flash arrays are much more dense than NOR. Indeed, since NAND flash is designed for the highest possible density, products typically use the smallest fabrication process nodes available, currently 16 nm.

The catch is that all memory devices have a certain amount of circuit overhead besides the memory cells — subsystems like row address decoders, sense amplifiers, bit line control circuits, peripheral I/O circuits, voltage regulators and I/O pads. The overhead area on a chip floor plan doesn't scale linearly with memory capacity. Reduce the size of memory arrays and the fraction of chip real estate devoted to peripheral logic increases. This even means using last generation's 25nm process geometry, the smallest feasible NAND device is one Gbit. This is overkill for most wearable applications with the sweet spot of the market requiring 512 Mbit or less.

The limitations on reducing NAND capacity for a given process geometry also translates into physical packages that are too large for many wearable applications. For example, a 1-Gbit serial NAND device, which is designed to be a NOR replacement for some applications, uses a 9 x 11 mm, 63-ball grid array package. In contrast, the smallest serial NOR 512-Mbit and 1-Gbit NOR products come in 4 or 5 x 6 mm packages, less than a third the size of NAND alternatives, and making them a much better fit for the tiny circuit boards powering wearables and other connected sensors in the IoT ecosystem.

NOR flash can also be stacked in a multi-chip package (MCP) with pseudo-static PSRAM to provide applications currently using SRAM embedded on a controller chip more capacity than the 1 Mbit commonly available on those SoCs.

For example, a 52-ball MCP with 64 Mbit NOR flash and 32 Mbit of PSRAM is only 4 x 6 mm, and higher density MCPs with up to 512 Mb NOR flash and 128 Mb PSRAM is only 8 x 8 mm (Figure 1 ). While this is probably overkill in both capacity and power consumption for most wearables, it could be applicable for devices that record video like glasses or mobile sensors.

Figure 1: Micron NOR Flash MCP size comparison

Rethinking system design for wearables and IoT
The space, power and application requirements of wearables and other mobile connected devices that collectively make up the growing IoT ecosystem require a fresh approach to system design, emphasizing integration, both on-chip (SoC) and in packaging (MCP/multi-chip package), faster boot times, and lower standby power.

Collectively, these design constraints make wearables look more like high-performance feature phones than smartphones or tablets. This means system designers can't simply down-scale existing mobile device platforms, but must take a fresh approach and optimize component choices for system requirements. NOR flash with next-generation high-density 0.4mm pitch packaging and MCP modules are a great fit for most wearable applications and offer more than adequate local storage capacity, execute-in-place convenience for application code, and low standby power to extend device battery life.

With IoT systems automatically offloading collected data to cloud-based repositories, the need for local storage on wearables is minimal, meaning the benefits of NOR flash far outweigh any compromises in memory capacity. While higher-end wearable devices, particularly those storing video, may still require NAND flash chips or eMMC modules, NOR flash memory is well positioned to serve the majority of the wearable and IoT device markets.

Howard Sian is Senior Business Development Manager, Wearable Solutions, at Micron Technology, Inc. He joined Micron in 2011 and has nearly 15 years of experience in the consumer electronics and semiconductor businesses. Before joining Micron, Howard was global technical account manager at Numonyx, where he managed the memory solution needs of a $500-million-a-year wireless account. Before that he was a senior applications engineer at Intel, where he was responsible for the technical alignment between Intel’s flash products to the requirements of leading wireless chipset manufacturers. He holds BSEE and BSCS degrees from the University of California, Los Angeles.

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