Is EDA stuck between a rock & a soft place? -

Is EDA stuck between a rock & a soft place?

The quandary facing those with a seemingly irresolvable dilemma is oftendescribed as being caught “between arock and a hard place .” However, the dilemma facing IC designers and thesuppliers of their electronic design automation (EDA) hardware tools is probablybetter described as being caught “between a rock and a soft(ware)place .”

IC developers have pushed transistor geometries down tothe tens of nanometers to increase the gate functionality of their designs. Thishas allowed the construction of impressive multicore-based system-on-chipdesigns that increase functionality beyond what anyone could even imagine just afew years ago. But just as the internal combustion engine requires fuel to powerit, complex multiprocessor SoC designs need software to run them – lots of it -and it must be developed in close coordination with the evolving hardwaredesign.

This fact came home – again – to roost, at the Design AutomationConference (DAC) this past week and the Embedded Systems Conference in May. In aDAC video , EDN/ESD editor Ron Wilson capturesthe essence of the situation facing IC designers.

At both shows numerouspanels and classes were devoted to the topic. At ESC, EDA vendor Cadence showedits System Development Suite for hardware/softwareintegration, and at DAC, competitor Mentor Graphcs touted its new Common Embedded SoftwareDevelopment . This is not the first time such efforts have beenattempted, as evidenced in the design articles included in a recent Tech Focus Newsletter. But will it takethis time? Will a truly useable integrated hardware/software framework emerge?

In addition to Down and dirty with hardware/software design, thefirst in a series of articles this week by Wayne Wolf, other articles on I’veincluded as my Editor’s To Picks on this vital topic include:

HW/SW co-verification basics
Breathing life into hardware/software codesign
Approaches to accelerated HW/SW coverification.

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