ISE 12.2 improves partial reconfiguration design flow -

ISE 12.2 improves partial reconfiguration design flow


ISE Design Suite 12.2 from Xilinx includes a fourth generation partial reconfiguration design flow and improvements to its intelligent clock gating technology deliver a 24 percent reduction in dynamic block-RAM (BRAM) power consumption in Virtex-6 FPGA designs.

A low-cost simulation solution for the embedded design flow is also now available in the latest release of the ISE Design Suite.

Partial reconfiguration enables on-the-fly flexibility that can expand the capabilities of a single FPGA. While operational, designers can reprogram regions of the FPGA with new functionality without compromising the integrity of the applications running in the remainder of the device.

Partial reconfiguration also enables designers to manage power consumption by swapping out high-power consuming functions for more power-efficient functions when the highest performance is not required.

The latest intuitive design flow and interface includes an improved timing constraint and timing analysis flow, automatic insertion of proxy logic to bridge static and reconfigurable partitions, as well as full-design timing closure and simulation capabilities.

ISE 12 enables designers to target Virtex-4, Virtex-5 and Virtex-6 devices for Partial Reconfiguration applications.

Xilinx has also enhanced its intelligent clock-gating technology, which was made available through acquisition of PwrLite Inc. in summer 2009, to enable the lowering of BRAM dynamic power. Through a unique set of algorithms, ISE can automatically neutralize unnecessary logic activity.

This is a primary factor behind power dissipation, as it enables power optimizations that were not applied at the RTL level to be implemented downstream after synthesis, thereby reducing overall dynamic power consumption by as much as 30 percent.

Starting in ISE Design Suite 12.2, the intelligent clock-gating optimization will also reduce power for dedicated RAM blocks in either simple or dual-port mode. These blocks provide several enables: an array enable, a write enable and an output register clock enable. Most of these power savings will come from using the array enable.

ISE offers fine grain clock gating optimizations integrated to the place and route algorithms.

ISE Simulator (ISim) is now available for the embedded design flow through the Xilinx Platform Studio (XPS) and Project Navigator tools, enabling embedded designers to take advantage of the mixed language (VHDL and Verilog) simulator integrated with the ISE Design Suite.

The latest version of ISim has several additional productivity-enhancing features, including automatic detection and listing of design memories for viewing and editing. This Memory Editor enables designers to explore what-if scenarios using a graphical way to force a value or pattern on a signal without needing to recompile the design. ISE 12 also makes it possible for designers to navigate to HDL source from the waveform viewer.

ISE Design Suite 12.2 is immediately available for all ISE Editions and list priced starting at US$2,995 for the Logic Edition. Fourth generation Partial Reconfiguration can be purchased as an option and is bundled with two days of onsite training.

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