Isolating SPI in high bandwidth sensor applications -

Isolating SPI in high bandwidth sensor applications

Editor’s Note: Mark Cantrell and Bikiran Goswami look at the Serial Peripheral Interface Bus (SPI), its constraints, and how to deal with those constraints in isolated systems using the company’s ADuM3150 in high bandwidth sensor applications.

SPI (Serial Peripheral Interface) busses are a favorite of designers for many reasons. The SPI bus can run at high speed, transferring data at up to 60Mbps over short distances like between chips on a circuit board.

The bus is conceptually simple, consisting of a clock, two data lines, and a chip select signal. Since data is presented on one phase of the clock and read back on the opposite phase, there is a lot of margin for delays and mismatches in speed. Finally, since the SPI bus is composed of unidirectional lines, it simplifies the implementation in a microprocessor by eliminating flow-control issues. As most traditional isolation devices are unidirectional, the SPI bus lends itself well to isolation using optocouplers or digital isolators.

In industrial applications such as thermal or pressure monitoring systems, communication with the ADC in the sensor front end does not require a high sample rate and hence a high SPI clock rate. Even isolated designs are simple to implement in a wide variety of isolation technologies.

But requirements evolve with time, and the venerable SPI interface has been pushed to its limits by applications with long wire runs, high data rates, and isolation requirements on top of it all. In this article we will look at the SPI bus, its constraints, and how to deal with them in isolated systems.

An application that pushes the limits of isolated SPI performance is high dynamic range sensor interfaces. To create a system with wide dynamic range a designer would start with an analog to digital converter (ADC) with a good signal-to-noise ratio (SNR), which is usually related to the word length. 16-bit words are common, and where higher dynamic range is required, other techniques can be employed such as variable gain amplification of the input and oversampling. Oversampling will trade bandwidth for noise rejection.

If the sample frequency is doubled, typically the noise performance is improved by 3 dB. So, for example, a 75x oversample rate will give an improvement in noise performance and dynamic range of about 18 dB. A 75x oversample of a signal means that an ADC running at 900 ksps would give 18 dB better dynamic range over about a 6-kHz band width. The bandwidth and dynamic range can of course be traded off, but in the end, running the ADC as fast as possible has great benefits.

This implies that the SPI bus will have to keep up with this avalanche of data. Let’s consider an example with a typical component used for high sample rate applications, such as the ADI AD7985 pulsar ADC, which can run up to 2.5 Msps. We’ll see how communicating with it through an SPI bus affects the performance of the signal chain.

ADC interfaces
The typical ADC handles data in two basic operations (Figure 1 ). First the ADC has a conversion period (tCONV ) in which it creates a digital word that represents the voltage at its input. The ADC then transfers this word through a digital interface to a controller during the acquisition time (tACQ ). The ADC usually has a minimum cycle time (tCYC ) before it can start another conversion, which is approximately the sum of tCONV and tACQ . Sometimes tCYC is shorter, if the ADC has special transfer modes that let acquisition and transfer overlap. For simplicity the following discussion assumes sequential conversion and acquisition.

Figure 1: Simple ADC transfer sequence

The conversion time and minimum cycle time are the same no matter how the data is transferred. But the acquisition time depends on the properties of the data interface, in most cases the operation of the SPI bus. If the acquisition time is lengthened due to SPI clock rates, the sample rate of the ADC can be severely limited.

SPI clock rate limitations
The SPI link between a microprocessor/FPGA (MCU) and an ADC is illustrated in Figure 2 . The SPI bus consists of the connections between a pair of shift registers, one in the master MCU and one in the slave ADC. The MCU provides a clock that synchronizes the transfer. One edge of the clock shifts data out of the shift registers, and the complimentary edge clocks the data that has been presented into the other end of each shift register in a ring topology. In the case of an ADC there may not be a need to shift data from the MCU to the ADC, so this channel has been eliminated for simplicity, along with the slave select. The ADC fills its internal shift register during the conversion phase of operation, and then shifts the register out during the acquisition phase.

Figure 2: ADC SPI communication block/timing diagram

In an SPI transaction the clock signal generated by the master travels to the slave through some wiring delays where it triggers the slave to shift out its data after some internal delay. The data signal travels back to the master again through wiring delays where it must arrive at the master in time for the complementary edge of the clock. The master typically has some additional setup time requirements.

Figure 2 shows how these delays establish the minimum time for half of a master clock period. In non-isolated systems these delays are typically very short, in most cases <10 nS, allowing the SPI clock to run at speed in excess of 50 MHz. If an isolation barrier is added to the SPI data path (Figure 3 ) it adds propagation delay (prop delay, tpISO ) terms to the trace delay. Isolator prop delays can be in excess of 100 nS, depending on the isolation technology used. Figure 3 shows how the extra isolator delay times extend the time required for a data transaction and significantly increase the minimum required half-period of the SPI clock. The isolation delays dominate all other time delays in the system and the maximum clock frequency can drop to a few MHz.

Figure 3: Isolated ADC SPI communication block/timing diagram

The primary constraint on the clock period is the requirement that data be present at the master before the next clock edge. In non-isolated systems this is not much of a constraint, and it actually adds to the robustness of the data transfer by allowing generous timing margins. However, once the propagation delay of the data path starts to dominate the half period, it severely degrades the maximum speed of the bus, limiting maximum throughput in isolated systems with long isolator propagation delays.

Luckily there is a way around this limitation. If the data returning from the slave has an independent clock synchronized to it, a separate receiving shift register can be set up in the MCU to accept data based on the independent clock. In this case the throughput of the SPI bus is no longer limited by the propagation delay of the isolation barrier, but by the throughput of the isolator.

Figure 4: Isolated system creating an independent data clock

The independent clock, DCLK, can be created easily by adding a data channel to the isolator and sending a copy of the isolated SPI clock alongside the ADC data (Figure 4 ). The isolator delays in the ‘SPI clock’ path match the isolator delays in the ‘ADC data’ path, effectively preventing isolator delays from limiting minimum required SPI clock period. Instead the period is constrained only by the shorter delays, shown in Figure 2, that would also constrain a non-isolated version of the system. So this approach enables faster SPI clocks, but has the disadvantage of requiring an additional isolation channel and an independently clocked shift register in the MCU. The MCU reads data from the secondary receiving register rather than the standard SPI register.

To illustrate how this data transfer method can be implemented in different technologies, the following three examples are examined quantitatively for maximum speed and qualitatively for power consumption and required board space. We will see that while in standard isolated SPI it is the round trip propagation delay that limits the speed, in the delayed clock scheme it is the timing skew and distortion in the isolator that sets the limit.
Optocoupler implementation
In typical industrial applications,single-channel digital optocouplers are frequently used in isolatinghigh speed buses. Four optocouplers are needed to isolate a standard4-wire SPI bus. The timing parameters important in estimating the maxSPI clock speed in a popular industrial CMOS optocoupler are:

  • Maximum data rate of 12.5 MBPS or a minimum pulse width of 80 ns.
  • Maximum propagation delay (tpISO) of 40 ns.
  • Maximum pulse width distortion (PWD) of 8 ns.
  • Maximum part to part propagation delay skew (tPSK) of 20 ns. This parameter is important since multiple optocouplers are used to create the isolated SPI bus.

To estimate the SPI throughput, we assume sometypical delays for the different components in Figure 3. Each tracedelay is assumed to be 0.25 ns, amounting to a total trace delay (tTRACE ) of 1 ns. Similarly, the slave delay (tSLAVE ) and master setup delay (tMASTER ) are assumed to be 3 ns and 2 ns respectively.

Therefore,from our discussion of isolated SPI clock rate in Figure 3, for a SPIbus isolated using the above optocoupler half the SPI clock period willbe ≥ [tTRACE +tSLAVE +tMASTER +2*tpISO ]ns or 86 ns, giving a maximum allowed SPI clock rate of 5.75 MHz. Thelong isolator prop delays considerably reduce the achievable SPI busspeed.

Now, consider adding an extra isolator in the reversedirection to route the isolated clock signal back to the master andimplement the delayed clock as shown in Figure 4 . This allows usto generate a clock signal in sync with the returned data from theslave. The round trip propagation delay [2*tpISO ]of the isolator no longer limits the clock rate. With the remainingdelays in the system, can the isolated SPI half clock period be ≥ [tTRACE +tSLAVE +tMASTER ] ns or 6 ns, supporting a maximum SPI clock rate of 80 MHz? Unfortunately, the answer is not that simple.

Figure 5: Practical DCLK timing diagram

Asymmetries in forward and reverse channels must still be accounted for when calculating the minimum SPI clock period shown in Figure 5 as tSKEW. The propagation delay skew between parts and the pulse width distortion limit the new SPI half clock period to ≥ [tTRACE +tSLAVE +tMASTER +2*PWD+2*tPSK ]or 62 ns. This results in a real maximum clock rate of 8 MHz. However,due to its 80-ns minimum pulse width limitation, this optocoupler canonly support a maximum SPI clock of 6.25 MHz. The above exampleillustrates that even if the optocoupler wasn’t constrained by itsminimum pulse width, the tSKEW severely limited the maximum SPI clock rate from a possible 80 MHz witha perfect delay match to 6.25 MHz in the actual application.

Canusing a faster optocoupler with a shorter minimum pulse width help? Avery high speed optocoupler with a minimum pulse width of 20 ns canallow us to run the previous interface at a higher rate. But even thesedevices suffer from large skew and distortion parameters. With a tPSK of 16 ns and PWD of 2 ns, the minimum SPI clock half period turns outto be ≥ 42 ns, resulting in a maximum clock rate of 11.75 MHz. In bothcases, the timing characteristics of the optocouplers further degradeover time, thereby introducing more mismatches between delayed clock andslave data. Adding timing margin for these variations results inrequiring further reduction of SPI clock rate.

Using anadditional fast optocoupler for SPI isolation, besides being expensive,also demands a lot of board area since these devices are typicallysingle channels in SO8 packages and 5 channels are required. The powerbudget for the isolated interface can be as much as 20 mA of current perchannel.

Digital isolator implementation
Over the pastdecade a new generation of digital isolators has becomeavailable. These devices have higher integration, higher speed, lowerpropagation delay, low skew, and less distortion. Consider aquad-channel digital isolator. The three forward channels and onereverse channel allows compact isolation of a four-wire SPI bus. Similarto the optocoupler example, we obtain the following timing parametersfrom the datasheet: minimum pulse width of 11.1ns (90 MBPS), maxpropagation delay (tpISO ) of 32 ns,max pulse width distortion (PWD) of 2 ns and max propagation delay skew between parts (tPSK )of 10 ns. But, unlike the single channel optocouplers, in aquad-channel digital isolator the channel-to-channel matching between apair of opposing directional channels also needs to be considered. Inthe above part, this parameter (tPSKOD ) is 5 ns.

Usingthe same typical delays for Figure 3, the half clock period for anisolated SPI bus using the digital isolator should be ≥ [tTRACE +tSLAVE +tMASTER +2*tpISO ] ns or 70 ns, a maximum clock of 7 MHz.
Likethe optocoupler case we see the SPI rate to be heavily constrained bythe propagation delay of the isolator. But digital isolators, built instandard CMOS technology, have stable timing characteristics acrossproduct lifetime. This lets us set the SPI clock rate without leavingmuch margin for variations in the timing characteristics.

Consider implementing a delayed clock with an extra isolator channel as per Figure 4 – at a minimum an additional high speed channel needs to be used. Thisprevents isolator prop delay from limiting overall SPI throughput, andnow a faster SPI clock is possible that’s limited only by mismatches anddistortion between the clock and data channels, plus trace, master, andslave delays. Given similar timing through all isolator channels, thenew SPI half clock period should be ≥ [tTRACE +tSLAVE +tMASTER +2*PWD+tPSK +tPSKOD ] ns or 25 ns, for a maximum clock rate of 20 MHz.

Inmany applications, the MCU only shifts out data from an ADC and doesn’tshift in anything. In such three-wire SPI buses, a single quad digitalisolator with two reverse channels can be used to implement the SPI busand the delayed clock. In these cases there is an added benefit. Thehalf SPI clock period will be ≥ [tTRACE +tSLAVE +tMASTER +2*PWD+2*tPSKOD ] ns or 20 ns, resulting in an even faster maximum clock rate of 25 MHz.

Althoughthe speed and skews of the digital isolators are significantly betterthan that of optocouplers, timing skews and distortions between channelsstill limit the maximum possible SPI clock rate. The extra isolator todelay the clock still consumes around 20-25% more power. Thus, usingexisting isolators will cost more power and board space while stillfalling short of the maximum possible benefit of the scheme.

Optimizing the digital isolator delayed clock implementation
AnalogDevices has developed a digital isolator optimized to deliver thehighest possible performance in the delayed clock scheme. The ADuM3150 (Figure 6 ) is part of the SPIsolator series of high-speed digital isolators designed to optimize the isolation of SPI buses.

TheADuM3150 generates a delayed clock, DCLK, without the use of an extraisolator channel. The DCLK is generated by delaying the standard SPIclock by an amount equal to the round trip propagation delay [2*tpISO]through the isolator. Figure 6 shows the internal block diagram of theADuM3150. The delay cell is carefully trimmed at production to match theround-trip prop delay through the part, thereby minimizing the timingmismatch between delayed-clock and returning slave data. The delaymismatch is not only considerably minimized but also well defined acrosswide operating conditions and is guaranteed in the datasheet by theDCLKERR parameter.
Figure 6: ADuM3150 SPIsolator Delay Clock Implementation

The DCLKERR is a measure of how much the delayed clock is out of sync with the slave data and therefore the sign of the DCLKERR indicates whether the delayed clock leads or lags slave data. Since thedelayed clock is used to sample the slave data into the master, itshouldn’t lead the data. DCLK lagging the data is acceptable as long asit doesn’t miss sampling the data bit altogether. The ADuM3150 datasheetspecs the DCLKERR between -3 ns and 8 ns and the PWD at 3 ns. Accounting for maximum leading DCLKERR and PWD, the SPI clock rate is ≥ [tTRACE +tSLAVE +tMASTER +(min)|DCLKERR |+PWD]ns or 12 ns, a maximum clock rate of 40 MHz. ADuM3150, with a maximumdata rate of 40 MHz is able to match this high SPI clock rate withoutany of the size, cost, and power penalties associated with using anextra isolator channel.

Table 1: Comparison of technologies

Inorder for oversampling to be a useful tool in increasing dynamic rangein sensor applications, there must be a high enough multiplier of thesampling frequency compared to the frequency of interest to providesignificant noise reduction. The delayed clock scheme presented hereprovides a path to improving the throughput of an isolated SPI interfaceand increase sample rates.

This method will provide a boost tothe max SPI clock rate across the available isolation technologies. Thedigital isolation technology provides significant advantages over theolder optocoupler because of the tight control of skew between channelsand other distortions in the signal chain.

Mark Cantrell is a staff applications engineer for the iCoupler Digital Isolator Group at Analog Devices, Inc. (ADI). His area of expertise is iCoupler digital isolation products,including isoPower isolated power supply devices and communications busdevices such as I2C and USB isolators. He is also responsible for agencysafety certifications for all iCoupler digital isolator products. Markreceived his MS in physics from Indiana University. He can be reachedvia email at .

Bikiran Goswami is a mixed-signal integrated circuit design engineer for the iCoupler Digital Isolator Group at Analog Devices, Inc. (ADI). His area of expertise is in designing iCoupler digital isolationproducts aimed at the standard data isolation devices and communicationbuses. Bikiran received his MS in Electrical Engineering from StanfordUniversity. He can be reached via email at .

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