ISSCC preview: Revving ReRAMS, boosting memory bandwidth - Embedded.com

ISSCC preview: Revving ReRAMS, boosting memory bandwidth

SAN FRANCISCO–Relentless scaling advances will highlight memory papers at February's International Solid State Circuits Conference here, but it may be break-throughs in off-beat memory architectures that raise a few eyebrows.

ISSCC, scheduled for Feb. 17-21, 2013 at the Marriott, features a slightly smaller percentage of memory papers than usual for the five-day affair (9 percent of the total is down from 10 percent this year and 10 pecent in 2011), but the topics are no less fascinating.

Memory subcommittee chair Kevin Zhang of Intel notes in his memory overview: “We continue to see progressive scaling in embedded SRAM, DRAM, and floating-gate based Flash for very broad applications. However, due to the major scaling challenges in all mainstream memory technologies, we see a continued increase in the use of smart algorithms and error-correction techniques to compensate for increased device variability.”

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