SHEFFIELD, England Jennic is changing its market approach, shifting from being solely a supplier of intellectual property to a fabless manufacturing business model, providing ICs directly to customers.
The move is seen as the first step in becoming a market leader for wireless-enabled sensor and control networks. It also follows the company’s launch earlier this year of the an IP portfolio for the IEEE 802.15.4 and ZigBee protocols.
To support the company’s expansion into fabless manufacturing, and develop the worldwide customer support network associated this approach, a third round of private funding supported by current investors is in progress.
Jennic’s integrated device will include radio, microcontroller and peripherals. It will secure battery-based wireless transmission for sensor and control applications, including residential and industrial control, personal health care, computer/gaming peripherals and consumer electronics.
The company said its strategy shift is driven by customers who want to reduce time-to-market by eliminating the need to develop and prove their own ICs.
Jim Lindop, Jennic's CEO and founder, said, “We have a clear lead in single-chip integration for this market and we intend to capitalize on this lead by adopting a fabless model. We have demonstrated functional first silicon to strategic customers, we are working with world-class manufacturing partners and will be delivering quantities approaching cellular phone numbers by the end of the decade.”
“While the transition to the fabless model in the wireless connectivity market represents a great opportunity for us as a company, we will continue to support our IP customers for wireline products such as physical layer framers, access co-processors, line-card connectivity, and other IP. This has been, and continues to be, an important part of our revenue stream,” added Lindop.
Since launching the IP portfolio in February 2004, Jennic has been an active member of the IEEE 802.15.4 and ZigBee standards committees.
The company’s Serial RapidIO IP core is also being tested and evaluated by NEC Electronics. It will incorporate NEC's SerDes and a range of test and diagnostic capabilities into their Serial RapidIO IP core, which will then be implemented in a test chip using NEC’s ISSP structured ASIC technology. The test chip will then be used to undertake compliance and interoperability testing with products from other members of the RapidIO Trade Association.
Jennic's RapidIO IP product line provides a range of integrated RapidIO interface solutions for a number of applications, including endpoints and switches. They are based around a common, modular architecture and implement the Physical, Transport and Logical Layer RapidIO standards.