Jitter considerations when matching timing solutions to your applications

Whether you are sitting at a computer, working on a tablet, talking or surfing on a cell phone, sending data over a network, performing digital signal analysis, or controlling an industrial robot, crystal oscillators or clocks embedded in all these products deliver stable clock signals that provide the heartbeat of just about every digital product. These products also span a wide range of frequency and stability requirements depending on the industry they are employed in.

For example, telecommunication, network systems, and test systems have some of the most stringent specifications for frequency stability and low jitter, while personal computing, medical instruments, and industrial systems also have tight specs, but not quite as tight as the first grouping. Lastly, consumer products such as audio/video systems, appliances, smart home and wearable fitness devices have, perhaps, the least stringent clock stability and jitter requirements.

Many embedded processors and microcontrollers have on-chip clock generators that just require an external crystal to provide a relatively-stable clock signal. However, if timing accuracy and low jitter are critical for the system, the on-chip clock generator can be bypassed and an external clock source can be added to provide a more stable, lower jitter signal. In many systems, the processor is only one of many ICs that require a clock signal – and to meet such system needs, a clock generator that delivers multiple clock outputs, each configurable to meet the needs of each of the timing requirements for the other chips can be used. Such a solution can end up replacing multiple crystals, thus saving board space, reducing power consumption, and lowering system cost, and, of course, providing more accurate and stable clock signals.

Jitter Basics
When transmitting a digital bit stream (a clock timing signal or a serial data stream) between two points, small variations in that timing signal due to imperfections in the transmitter, the channel, or the receiver, cause slight shifts in the signal timing. These timing errors are referred to as jitter (Figure 1). There are some common definitions of jitter that appear in various specification documents. For example, in the SONET communications specification jitter is defined as the short-term variations of a digital signal’s significant instants from their ideal positions in time (a significant instant might be the optimum sampling instants). Alternately, in the Fiber-Channel specification, jitter is defined as the deviation from the ideal timing of an event. The reference event is the differential zero crossing for electrical signals and the nominal receiver threshold power level for optical systems.

Figure 1. Jitter shows up in a digital signal as a deviation from the ideal event timing and can be either a negative amount that shortens the unit interval, or a positive value that increases the unit interval.

Although the two definitions have some differences, they both have a common fundamental point – jitter has to do with the time difference between the ideal and actual occurrence of an event. That event could be the rising and falling edge of a clock signal, the optimum sampling instant of an NRZ encoded data stream, the zero-crossing of a differential signal, or some other event. Jitter can also be considered as unwanted phase modulation of a digital signal. Thus jitter characterization is essential for guaranteeing an acceptable bit-error-rate (BER) for the system since the jitter can affect timing margins and synchronization, as well as potentially causing still other problems.

Jitter can be classified into two basic types – random jitter and deterministic jitter. Random jitter (RJ) is unpredictable and is characterized by a Gaussian probability density function. When viewed using an eye pattern, the RJ shows up as “fuzziness” in the switching waveform (Figure 2a). Deterministic jitter (DJ) can be predicted (as long as one knows the bit stream characteristics), and has definite amplitude limits, and in an eye pattern, it shows up as discreet bands in the switching waveform (Figure 2b). RJ is caused by thermal or other random noise effects that occur in the system and these thermal effects are induced into the phase of the clock and data signals. DJ is a result of process or component interactions in the system, such as the effect of limited bandwidth on specific patterns of 0’s and 1’s in the serial bit stream. Thus, jitter is an important performance measurement for both clock and data signals in a serial link. Jitter in different parts of the serial link is additive and can thus increase the total jitter such that data errors can occur when the event timing points shift past the intended boundary.

(a) (b)
Figure 2. Eye patterns help visualize the effect of jitter on the digital switching signal. For random jitter, the effect appears as a “fuzziness” signal waveform (a), while for deterministic jitter, the effect appears as discrete “bands” in the switching waveform (b).

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By definition, jitter is a measure of time, and is often measured inpicoseconds. However, jitter is often normalized to a term called theunit interval (UI). This jitter (UI) is calculated by dividing jitter(measured in ps), by the time for one UI (in seconds). In addition tothe DJ and RJ jitter types, when analyzing the effects of jitter on asystem, the instantaneous jitter, as well as the average andpeak-to-peak jitter, are important aspects to include in the systemanalysis.

Jitter is based on the timing of a specific event. To find the instantaneous jitter, let’s start by calling the event K , and the time that it actually occurs, tK . Since the event, K , is often a repeating event, the nth occurrence of K can be represented as K n , and the time of the nth occurrence as tK {n}. By subtracting the actual tK {n} from the ideal tK {n}, the result is the instantaneous jitter associatedwith the nth occurrence of the event. To compute the average jitter,root-means-square calculations are done on an uncorrelated sequence ofinstantaneous jitter measurements to derive the rms average values. Andpeak-to-peak jitter for a set of N instantaneous jitter values iscalculated by subtracting the minimum instantaneous jitter measurementresults from the maximum instantaneous jitter results. 

Jitter can also be subdivided into various types – duty-cycledistortion (DCD), which is often referred to as pulse-width distortion(PWD), and data-dependent jitter (DDJ), which is also called intersymbolinterference (ISI) or pattern-dependent jitter (PDJ). DCD/PWD is oftencaused by voltage offsets between differential inputs and differencesbetween the rise and fall times of the digital signals. DDJ is atime-domain result that appears in a system when the pattern of the bitsbeing sent changes from a typical square-wave clock signal to anon-clock pattern. Thus, the amount of jitter will be different for eachunique bit pattern.

Jitter control
Now that basic jitter terms aresomewhat defined, let’s look at how the jitter can be kept under controlto minimize its effect on the data and on the entire system. There aretwo basic approaches – first, design the circuits so they are moretolerant to variations in the clock signals or data streams, or second,use a very stable clock source that delivers very-low-jitter signalsthat are well within the systems jitter specifications. Of course, thecombination of both approaches will yield the best results – it’s just amatter of the cost tradeoffs of the precision timing source, and thedesign cost for the jitter-tolerant circuits.

As mentioned earlier systems can be categorized based on theirtypical jitter requirements, with telecommunication and high-speednetworking systems demanding the tightest jitter specifications – oftenbelow 1 ps. Computer systems, medical and industrial systems can oftendeal with jitter in the 1 to 4 ps range, while consumer products, homeautomation, fitness products and similar devices have still lessstringent requirements. Table 1 sums up some the basic requirements forthe various equipment groupings.

Atypical system circuit board such as found in a network switch, router,or even a set-top box, often contains multiple complex digital circuitsthat operate at internal clock speeds of several Gigahertz. An externalclock signal of 50 to a few hundred Megahertz will typically providethe basic timing and then internal phase-locked loops will typicallymultiply the frequency up to the desired internal clock. To distributethe clock signals, a clock tree will connect all the circuits to one ormore clock signals of different frequencies so that each circuit can runat its own specified clock speed. However, when the clock signal ismultiplied internally to the desired frequency, the jitter is alsomultiplied and that makes it all the more critical that designers startwith a low-jitter source.

Designers face many pressures in crafting high-performancesystems, and those pressures are often contradictory – shrinking clockperiods in high-speed systems such as 10 Gbit Ethernet, or networkpacket processing demand ever-tighter jitter requirements to maintainsystem performance. However, at the same time increasing systemcomplexity and density can complicate thermal management (thermalchanges can also contribute to jitter), while system designers faceincreasing pressure to reduce system costs, board area and power.Additionally, the increased system complexity makes it more important togive designers more options to support multiple programmablefrequencies that can support last-minute design changes or multiplesystem configurations.

Timing Solutions
Clock generator ICs come in awide variety of configurations that, typically, can provide one to eightoutputs, some with fixed frequency outputs, others with configurableoutputs that allow designers to adjust the frequency, deliversingle-ended or differential outputs, adjust logic levels, and more.Typical of the many choices, the IDT5P49V5901 is a multi-output,low-jitter (<0.7 ps RMS from 12 kHz to 20 MHz), programmable clockgenerator that can offer four output pairs that can each deliver anindependent clock signal of up to 350 MHz in any of a wide range ofinterface types --- LVPECL, LVDS, HCSL, and LVCMOS (Figure 3).

Figure3. The multi-output programmable clock generator, the IDT5P49V5901, candeliver output frequencies of up to 350 MHz and has a phase jitter of<0.7 ps RMS from 12 kHz-20 MHz.

The first chip in IDT’s VersaClock 5 family, the clock generation circuit can be programmed (or reprogrammed) using an I2 Cserial port while the device is operating in the system, thuspermitting designers to update system performance, overrideconfiguration parameters stored in the on-chip non-volatile memory, orperform tests at various speeds. Four banks of one-time programmablenon-volatile memory on the chip allow companies to pre-program fourdifferent frequency and output characteristics, thus reducing inventoryrequirements. Designers can leave programming for the last possiblemoment to ensure the most up-to-date parameters are loaded before asystem is shipped. Tools such as the company's Timing Commander helpsdesigners configure and program the VersaClock 5 devices using agraphical user interface.

For multi-channel devices in this class, a single clock input orcrystal can be used to generate the desired output frequency on eachoutput, with fractional output divider circuits on the chip driving eachoutput pair. The output pairs can operate as differential outputs orthey can be used as eight single-ended outputs. Able to replace up toeight crystals, the clock generator helps reduce board space, cost andsimplifies the bill of materials. The buffered copy of the referenceinput also eliminates an additional crystal.

With programmable low-jitter timing solutions, designers have theflexibility to address the multiple clock requirements of systemsranging from high-speed telecommunication infrastructure systems tonetwork infrastructure products such as switches and routers andhigh-performance computers and servers. However, determining the effectsof jitter on the system, as well as defining the jitter budgets for thevarious subsystems are the keys to optimizing system performance.Programmable multi-output clock generation circuits give designers manyoptions as well as the ability to reduce system cost, complexity, andpower.

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