In this Product How-To article, James Wilson of Silicon Labs describes the clocking requirements in next generation 10G to 100G networks using high speed optical links and how the company’s Si5374/Si5375 clock ICs can be used to satisfy the needs for any-frequency synthesis, jitter attenuation, clock generation and clock distribution.
Networking service providers are significantly expanding their transmission network capacity to meet the burgeoning demand for bandwidth-intensive video and web-driven multimedia applications.
This application-focused demand is driving the migration from 10G to 40G and 100G high-speed optical links in both core and metro applications. Innovation is required on multiple fronts to deliver this capacity expansion at the lowest possible total cost of ownership (TCO) while maintaining network reliability and quality of service.
This network migration is being enabled by several new and exciting technologies such as coherent optics, which supports 40/100G transmission over existing or new fiber while eliminating the need for external bulk dispersion compensation modules.
Additional innovation is happening on the IC front, with both existing and startup semiconductor suppliers introducing 4 x 28 Gbps transmit and receive circuitry, pushing the speed and performance envelope.
Significant advances in clocking technology are required to keep pace with these technical breakthroughs and to deliver an overall hardware solution that meets 40/100G system requirements.
These clocking solutions must have sufficiently high performance to work in core transmission networks, but also must be flexible enough to work in higher density line cards intended for metro transport networks.
This combination of performance and flexibility is especially important for metro applications, since metro networks are expected to gradually migrate to a mix of 10G, 40G and 100G systems.
Challenges in 40/100G Optical Line Card Designs
There are four key challenges for clock generation in 40/100G optical line cards: frequency flexibility, clock jitter, cross-talk mitigation and phased-locked loop (PLL) integration.
Since 40/100G systems often must support a variety of protocols, including OTU3, OTU4, 10GbE and 100GbE, they also require multiple reference frequencies. Table 1 below shows typical frequencies required by these 40/100G systems.
Table 1. Common 40/100G Reference Clock Frequencies (Rounded)
Note that many of these rates are fractional frequencies that must be generated precisely. The clock device must have high input jitter tolerance and be able to synchronize to a jittered backplane reference, gapped clock input (for OTN asynchronous demapping applications) or to a local oscillator.
This requirement puts an additional restriction on the clock IC, since its PLL must often be able to support an input frequency that is non-integer related to its output frequency.
In addition, 40/100G clocking circuits may need to support custom frequencies required by field-programmable grid array (FPGA) solutions (e.g., 322.265625 MHz) or proprietary forward error correction (FEC) rates. To synthesize these frequencies and ensure a high degree of frequency accuracy, developers must use clock ICs supporting any-rate frequency synthesis.
Ultra-low clock jitter is of paramount importance given the stringent jitter requirements for 40/100G systems. An excessive level of clock jitter due to the intrinsic jitter of the line card’s frequency source, the line card jitter attenuating clock, FPGA/ASIC internal phase-locked loops (PLLs) or jitter due to board-level noise sources can make it difficult to meet system-level jitter requirements.
The 40/100G PHY contributes clock jitter as well. Its externally provided reference must be internally multiplied using a phase-locked loop (PLL) to a higher frequency to clock the transmitter at its given line rate.
Excessive jitter within this internal PLL or the rest of the timing path reduces the jitter margin of the overall design. Given these considerations, it is recommended that a jitter attenuating clock or local oscillator with ultra-low jitter be used (<0.4 ps rms or less) as the 40/100G PHY reference clock.
Power supply noise also impacts clock jitter. First, switch mode power supplies induce ripple, which can increase jitter on oscillators and clocks. Second, power supply noise can be induced by FPGAs ASICs and other devices.
FPGA/ASICs typically have multiple wide output banks that are simultaneously switched. This switching induces fluctuations on the power rail that ripple through the power plane and couple into adjacent devices including clock ICs.
Careful power plane design, noise isolation between ICs and increased power supply decoupling can mitigate power supply noise. However, cost, PCB layout and design constraints may limit the number of techniques available to hardware designers.
As a general rule of thumb, timing devices with extensive levels of internal linear voltage regulation are recommended in jitter-sensitive applications including 40/100G systems.
Coping with Cross-Talk
Cross-talk between PLLs is another effect that must be carefully considered in 40/100G designs. Typically high-performance analog PLLs that are in close physical proximity to one another will experience some level of cross-talk.
Of particular importance is the physical proximity and relative orientation of each of the PLL voltage-controlled oscillators (VCOs). There are multiple forms of cross-talk or coupling including electromagnetic, direct coupling and indirect coupling. Direct coupling can occur when there are shared electrical signals among multiple PLLs.
Indirect coupling can occur when there is a modulation path connecting multiple PLLs. Insufficient noise rejection on clock device control signals can increase the risk of injection locking between PLL VCOs. The worst-case configuration is an application that requires multiple PLLs to operate at frequencies that are close in value to one another, but not exactly the same (i.e., plesiochronous).
Cross-talk is particularly important in multi-PLL clock ICs, given the close proximity of multiple PLLs and their respective VCOs. For example, if each PLL is configured to operate as an OTU4 reference, then each PLL will nominally operate at the same frequency.
However, given that each OTU4 clock frequency can vary by as much as ±20 ppm, some minor frequency differences will exist between the PLLs. This creates a challenging environment in that an application that requires ultra-low jitter generation and close physical proximity of multiple PLLs also may be susceptible to increased cross-talk.
Troubleshooting coupling problems at the PCB level is exceedingly difficult due to the myriad potential coupling mechanisms involved. In addition, development schedules are tight, and engineering resources are constrained, leaving little time for complex board-level debug.
A better approach is to perform cross-talk testing of multi-PLL clocks during the device evaluation process. The method entails configuring the multi-PLL device in a worst-case configuration from a cross-talk standpoint, and then measuring the resulting output clock jitter.
Measuring output clock jitter is an excellent proxy for cross-talk performance, since cross-talk effects will be manifested as increased clock jitter in the application.
Since output clock jitter heavily influences the 40/100G serializer/deserializer (SerDes) performance and the resulting bit-error rate (BER) of the system, cross-talk testing is a practical way of ensuring the design will meet system-level requirements long before the PCB design is completed.
Table 2 below shows two recommended cross-talk tests. The first cross-talk test accounts for the configuration when all optical ports are configured with the same protocol. The second test accounts for testing different frequency plans in the event that the design must support multiple protocols.
Table 2. Example Cross-Talk Tests
While frequency flexibility, clock jitter and cross-talk are important considerations, clock integration presents arguably the most challenging technical hurdle related to timing that must be overcome for 40/100G system designs. As 40/100G technology migrates from core to metro networks, optical port density will continue to increase.
This increases the need for multi-PLL jitter attenuating clocks that can perform line card clocking functionality, including hitless switching between clock references, frequency translation and jitter attenuation.
To help ensure that the design delivers cost savings and total cost of ownership (TCO) benefits in comparison to legacy 10G networks, the multi-PLL jitter attenuating clock must provide a lower cost-per-PLL than legacy 1-PLL solutions.
High-Performance Clock Solutions for OTN
Silicon Labs has leveraged its DSPLL technology to create the industry’s first family of high-performance 4-PLL clock ICs optimized for high-speed 10G, 40G and 100G optical transport networking (OTN) applications.
The Si5374/Si5375 clock ICs support any-frequency synthesis, jitter attenuation, clock generation and clock distribution at jitter levels of 0.4 picoseconds rms. Figure 1 below shows the Si5375 IC providing line card clocking for a 40/100G line card. The device integrates four independent, high-performance DSPLLs within a single device, providing 100 percent higher integration than legacy 2 analog PLL (APLL) solutions.
Figure 1. Quad DSP Clock Solution in 40G Networking System
The Si5374 has eight input clocks and eight output clocks. For applications requiring fewer inputs/outputs, the Si5375 has four input clocks and four output clocks. The Si5375 generates any output frequency (<808 MHz) from any input frequency (<710 MHz).
Each DSPLL can be used to generate a unique frequency, simplifying the design of multi-protocol line cards. Any combination of frequencies can be generated with ultra-low phase jitter (0.4 ps rms).
High-performance jitter-attenuating clocks such as Silicon Labs’ Si5374/75 4-PLL devices can meet the frequency flexibility, clock jitter, cross-talk immunity, clock integration and cost targets of 40/100G designs.
The Si5374/75 IC’s quad DSPLL architecture delivers comparable performance to discrete analog single PLLs, while providing superior cross-talk immunity and a higher level of clock integration.
PLL loop filters are integrated on chip, providing narrowband PLL jitter and wander filtering while improving noise immunity in comparison to legacy solutions that require discrete filters.
The highly flexible devices support simultaneous free-run and synchronous operation, enabling them to be used in mixed-mode systems. In addition, DSPLL-based clocks provide high input clock jitter tolerance and can connect directly to gapped clock inputs, critical for OTN asynchronous demapping applications.
Technical innovation is required on multiple fronts to enable the industry migration from 10G to 40/100G. Recent advances in optics, SerDes and clocking technologies are helping to pave the way for this network transition.
Given their direct impact on system-level performance, multi-PLL clocks should be evaluated in terms of frequency generation capabilities, jitter, cross-talk and gapped clock input tolerance early in the development process.
James Wilson is marketing director for Silicon Laboratories ’ timing products, overseeing the marketing program for the company’s clock and oscillator products. He joined Silicon Laboratories in 2002 as a product manager focusing on optical networking solutions. Previously, he worked at Freescale Semiconductor’s networking and communications systems group in Austin, Texas. Mr. Wilson holds a Bachelor of Science degree in mechanical engineering and a master’s degree in business administration from the University of Texas at Austin.
This article provided courtesy of Embedded.com Copyright © 2011 UBM–All rights reserved.