A large amount of uncertainty has permeated the digital domain in both the areas of design methods and engineering career paths. It comes as no surprise in today's cutthroat market that engineers are reluctant to commit precious time and resources to learning new skills without being certain what the future holds.
One thing we do know is that the EDA industry as a whole is poised to leap to new levels of design abstraction. Commonly referred to as electronic system-level (ESL) design, this design method encompasses both the languages used to represent designs at a very high level of abstraction and the appropriate synthesis technology that can transform these representations into their implementation-level counterparts.
When it comes to the algorithmic-intensive designs featured in digital signal processing (DSP) applications, the de facto standard domain-specific ESL language is MATLAB from The MathWorks. This language allows DSP algorithms to be captured concisely and simulated, visualized, and analyzed extremely efficiently.
It's important to understand that such designs do not involve a simple linear progression from the algorithmic domain (MATLAB) to the implementation realm (such as RTL). In reality, first the algorithmic space must be explored; then those results can be used as a starting point to explore the implementation space and ultimately perform further evaluations in the algorithmic domain; and so it goes Thus, using a flow that involves taking a MATLAB representation and then hand-coding a C, C++, SystemC, or RTL equivalent is doomed to failure.
What the industry needs is a way to take the MATLAB representation and automatically translate it into its RTL equivalent. So far, the optimum approach has been to use a library of predesigned and highly parameterized IP blocks that map onto core MATLAB functions, coupled with appropriate architectural-synthesis technology. The DSP architects, hardware-design engineers, or representatives from both domains can then define the IP-block parameters that will guide the architectural-synthesis tools. The fact that this synthesis is architecturally aware with regards to the target implementation technology (ASIC/SoC, structured ASIC, or FPGA) means that the ensuing RTL is highly optimized for the task.
So, although the future for digital design engineers may be scary—”languages, architectures, and algorithms, oh my!”—it's a lot less scary for DSP-centric designers. The state-of-the-art DSP design methods introduced here are no longer experimental—they're proven, robust, automated solutions. The end result is that DSP is truly at the forefront of ESL design. Design teams that embrace these new ESL design methods will see huge leaps in productivity and will push the EDA industry to the next level of design abstraction that will truly define the first new EDA era of the 21st century.
Vin Ratford is CEO and president of AccelChip Inc. and has served in executive management positions in the EDA and semiconductor IP industries for the past 25 years. You can reach him .