Lattice completes 2nd generation CPLDs - Embedded.com

Lattice completes 2nd generation CPLDs

Lattice Semiconductor has introduced the second, and smallest, member of its ispMACH 5000VG SuperBIG CPLD family. The ispMACH 5768VG, featuring 768 logic macrocells has been added to the 1024 macrocell ispMACH 51024VG device released last November.

This in-system programmable (ISP) logic family, which provides up to double the logic capacity of the company's ispLSI 5000VE devices, includes additions such as advanced I/O standard (GTL+, HSTL, SSTL, etc.) sysIO support and sysCLOC phase locked loops (PLLs).

Performance for the ispMACH 5768VG is specified at 5ns pin-to-pin logic delays (tPD) with an operating frequency (fMAX) of 178MHz, world-class performance for a device of this density.

The first member of the family is the 1024 macrocell ispMACH 51024VG device. Its performance is specified at 5ns pin-to-pin logic delays (tPD) with an operating frequency (fMAX) of 178MHz.

The ispMACH 5000VG family is supported by Lattice's ispLEVER Version 1.0 design tools. These tools maximise resource utilisation through timing driven placement and routing coupled with optimised synthesis support from vendors such as Exemplar and Synplicity.

Both devices are available in 256- and 484-ball fine pitch ball grid array (BGA) packaging featuring a 1mmball pitch.The release of this family represents the completion of Lattice's second generation of BFW (Big-Fast-Wide) products, consisting of the 3.3V ispMACH 5000VG, ispLSI 2000VE and ispLSI 5000VE families.

The devices from the ispMACH 5000VG family make use of the SuperWIDE macrocell architecture used in the company's ispLSI 5000V family. Logic capacities beginning at 768 macrocells are large enough to hold multiple functions commonly implemented in CPLDs such as bus bridges, memory controllers, and control logic.

The sysIO-capable pins of from 196 to 384 per device provided in the devices makes them suitable for wide bus interface applications.

The instant power-up capability of these devices makes them suitable for power-up sequence control in large, complex systems.

Each I/O pin on the ispMACH 5000VG devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces. General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 and 1.8V).

The LVTTL and LVCMOS 3.3 interfaces are 5V tolerant, supporting integration into legacy designs. Programmable drive levels for these standards enable the elimination of series termination resistors, reducing overall system cost.Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support. The ispMACH 5000VG family also supports GTL+, PCI, and PCI-X I/O configurations for use in high-speed bus interfaces.

The devices have two sysCLOCK PLLs that provide precise timing control for high-speed designs. Designers can generate complex clock waveforms with the clock multiply and divide capability of the PLL as well as adjust setup, hold and clock to output timings by shifting the clock under sysCLOCK control.

This family uses the SuperWIDE 68-input logic block that is found in other ispLSI 5000V devices, providing support for emerging 64bit applications. This SuperWIDE capability can lead to a 60% performance gain compared to devices with the more traditional 36-input logic block for complex logic functions.

Lattice has enhanced the ispMACH 5000VG logic block by increasing the maximum number of product terms per function from the 35 implemented in the ispLSI 5000VE series to 160.

This leads to further performance improvements, up to 25% faster than architectures that support a maximum of 35 product terms per function.

Third generation SuperFAST makes its entrance

First devices in Lattice's ispMACH 4000 third generationSuperFAST family are the the 256 macrocell ispMACH 4256 and the 512 macrocell ispMACH 4512. Both devices are available in 2.5- and 1.8V power supply versions.

The ispMACH 4000 family provides logic designers with a single architecture that covers a range of logic capacities, with 6 logic density options from 32 to 512 macrocells in a variety of package and I/O options. I/O counts range from 30 to 208 across the family. The devices provide optimal logic implementation for many glue logic, state machine, decoder, bridging, power-up, and signal handshaking functions. These functions are critical for the implementation of many high performance computing, communications, and industrial applications.

The ispMACH 4256 devices provide 3.0ns pin-to-pin delay, 3.0ns clock-to-output delay, 2.0ns set-up time, and 300MHz operating frequencies. The ispMACH 4512 devices provide 3.5ns tPD, 3.5ns tCO, 2.4ns tS and 256MHz fMAX.Future members of the family are expected to reduce pin-to-pin delays to 2.5ns and provide operating frequencies well above 300MHz.

The ispMACH 4000 devices have two I/O banks, each with their own power supply voltage that can be set at the appropriate voltage to support LVTTL and LVCMOS 3.3, 2.5, and 1.8V outputs. Device input buffers have programmable thresholds that support the above standards independent of the I/O bank voltage.

All ispMACH 4000 devices are also boundary scan testable and in-system programmable through an IEEE 1149.1-compliant JTAG boundary scan interface. The programming of the devices is fully compliant with the IEEE 1532 standard as well.

The ispMACH 4000 family is supported by ispLEVER design tools.

Published in Embedded Systems (Europe) February 2002

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