Lattice ECP5 FPGA family combines 40% lower-cost, 30% lower power, and 2X functional density in smallest package - Embedded.com

Lattice ECP5 FPGA family combines 40% lower-cost, 30% lower power, and 2X functional density in smallest package

Lattice Semiconductor Corp. announced its ECP5 family for small-cell, microserver, broadband access, industrial video and other high-volume applications where the lowest-possible cost, lowest-possible-power, and smallest-possible form-factor are crucial. The ECP5 Family ‘breaks the rules’ of conventional FPGA approaches to deliver a SERDES-based solution for designers to rapidly add features and functions to complement those delivered by ASICs and ASSPs, reducing development risk and quickly overcoming time-to-market challenges.

Lattice optimized the ECP5 family’s architecture with the goal of delivering the best value below 100k LUTs for performing critical functions as a companion chip to ASICs and ASSPs. Achieving 40% lower cost than competing solutions, optimizations include small LUT4-based logic slices with enhanced routing architecture, dual-channel SERDES to save silicon real estate, and enhanced DSP blocks for up to 4x resource improvements.

In wireless and wireline applications, the ECP5 family delivers an FPGA solution for enabling implementation of data-path bridging and interfacing in a small, low-cost package. ECP5 FPGAs provide the flexible connectivity required in outdoor small-cells, at extremely low-cost. They can also enable a smart SFP (small form-factor pluggable) transceiver solution for broadband access equipment, including integrated operation and maintenance, in a compact 10mm x 10mm package.

The company claims that the ECP5 family is the only FPGA portfolio in the industry that enables 85k LUTs and SERDES in 10mm x 10mm packages, amounting to 2X the functional density of competing solutions. Smart ball depopulation further simplifies package integration with existing PCB technology and reducing overall system cost.

Enhancements leading to 30% lower total power than other FPGA solutions include stand-by mode operation of the individual blocks including SERDES, dynamic IO bank controllers and reduced operating voltage. This enables single channel 3.25Gpbs SERDES functions starting below 0.25W, and quad channel SERDES functions starting below 0.5W for supporting a broad range of interface standards, including DDR3, LPDDR3, XGMII and 7:1 LVDS, PCI Express, Ethernet (XAUI, GbE, SGMII) and CPRI.

The ECP5 FPGA family is supported today in the Lattice Diamond Software Tool .

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