Lattice Platform Manager aims to cut BoM by 50 percent - Embedded.com

Lattice Platform Manager aims to cut BoM by 50 percent

CPUs, FPGAs and ASICs are used to perform the primary processing functions on many circuit boards and can require multiple board-mounted power supplies that need to be turned on and off in a specific sequence, monitored for faults and trimmed for voltage accuracy.  

In addition, the input power to the board often requires redundant power management and, in the case of plug-in boards, hot-swap functionality.  All the functions that control various power rails are collectively called power management.  

After all supplies are turned on, the system requires digital support functions such as reset distribution, start-up configuration control for FPGAs and ASSPs, watchdog timers and a system bus interface for a microcontroller.  These digital support functions are collectively called digital management.  

Power and digital management together are often referred to as board or platform management and Lattice’s Platform Manager family provides a single-chip solution that integrates all of these power and digital management functions.

The programmable Platform Manager devices are intended to simplify board management design significantly by integrating programmable analog and logic to support common functions, such as power management, digital housekeeping and glue logic.

The products are Lattice Semiconductor Corp.'s third-generation of mixed-signal devices. By integrating the support functions, Platform Manager devices can not only reduce the cost but also can improve system reliability and provide a high degree of design flexibility that minimizes the risk of circuit board re-spins.

Lattice expects the devices to be used applications such as wireless infrastructure, networking core equipment, server, data storage and high-end industrial instrumentation.

The Platform Manager product family consists of two devices, the LPTM10-1247 and LPTM10-12107.  The LPTM10-1247 device can monitor 12 voltage rails and supports 47 digital I/O, while the LPTM10-12107 monitors up to 12 voltage rails and supports 107 digital I/O.

Functionally, these devices include both a power management section and a digital board management section.  The power management section consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7 percent, a 48-macrocell CPLD, programmable hardware timers, a10-bit analog to digital converter and a trim block for the trimming and margining of supplies. 

The digital board management section consists of a 640-LUT FPGA and programmable logic interface I/O.

The traditional methods of designing with a collection of unique single-function ICs for power management, and complex design partitioning across multiple programmable devices for digital support functions, are simply replaced by the single chip Platform Manager device.  Lattice anticipates that in many cases the Platform Manager device can cut the bill-of-material cost by 50 percent.  

When implemented correctly, board power management can dramatically improve system reliability, because when operation under abnormal or faulty conditions is prevented, damage to components and corruption of system memory is avoided.  With the traditional approach to power management, designers often reduce the number of supplies monitored, the speed of response to errors and the accuracy of monitoring in order to meet cost targets, compromising board reliability.

The Platform Manager avoids this compromise with its low cost and ability to monitor up to 12 rails with 0.7 persent accuracy and a <65µs response to power supply faults. The Platform Manager product family will be supported by PAC-Designer 6.0 and the Starter version of ispLEVER 8.1 SP1 design software tools. To accelerate design time using the Platform Manager, Lattice will provide four free reference designs and three free IP cores that implement common functions such as fault logging into non-volatile memory, closed loop margining and interface to I2C or SPI bus masters. In addition, a Platform Manager design development kit, containing an evaluation board complete with demonstration code and documentation, can be purchased for $109.  This board allows users to see known good hardware in five minutes and to recompile the provided source code to get to a known good starting point in thirty minutes.   Platform Manager devices are available in commercial and industrial temperature ranges, and are available in environmentally friendly lead-free/halogen-free packages.  High volume pricing for the LPTM10-1247 device in a 128-pin TQFP package is $3.75.   A video demonstration of the Platform Manager can be viewed here.

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