Lattice revamps design tools to ease FPGAs use -

Lattice revamps design tools to ease FPGAs use


Lattice Semiconductor Corp. has carried a complete update of the design tools its supplies for use with its FPGAs. Version 1.0 of the Lattice Diamond FPGA design software provides as set of tools and a modern user interface to enable designers to more quickly target low power, cost sensitive FPGA applications.

Diamond will essentially replace the ispLEVER tools which Lattice will continue to support for FPGA design over the next 18 months while transitioning its FPGA customer base to the Diamond design environment. There are no changes to the ispLEVER Classic product, which targets CPLD and legacy FPGA devices.

Lattice has retained some of the features used in ispLEVER including an accurate power calculator, simultaneous switching output noise calculator, and the proven MAP and PAR FPGA implementation algorithms.

To improve 'what if?' design exploration Diamond software supports multiple design implementations with a design source being shared among implementations, or each implementation can have its own unique design source.

Different approaches can be tried to evaluate their effect on design size, cost, performance and power. Optimization options for logic synthesis and place and route are captured as a 'strategy' that can be applied to any of the implementations.

Diamond software comes with a library of pre-defined strategies, and users can also create their own and add them to this library. A single strategy’s settings can be updated, for example to an alternate PAR algorithm tuned for highly connected designs, and run against several unique implementations to determine if the results better meet the design goals for cost, power and performance.

A 'run manager' can launch a user-selected set of implementations to be run through the flow, exploiting multi-core processors, if available, to improve the elapsed time to final results.

Designers can manage their design view windows through the attach/detach feature. This feature allows the activation of many alternate concurrent design views across the available screen space, yet avoids the clutter that could result without advanced window management. Combined with the extensive cross-probing between Diamond Views, designers can investigate their design implementation’s utilization and critical timing.

Also included to improve designer productivity is built-in HDL visualization and code checking saves time by quickly catching coding errors and improving design documentation. Using a 'timing analysis view' navigation of the static timing results is eased and when timing constraints are revised, direct updates to timing analysis avoid the potentially significant time required to re-implement the design.

Diamond software also includes capabilities for scripting the design flow. Tool command language (Tcl) command dictionaries specific to the Diamond design environment are available for projects, netlists, HDL code checking, power calculation and hardware debug insertion and analysis.

The Diamond design environment is supported on Windows and Linux. It includes support for Windows 7, and under Windows 7 64-bit, the software has access to a full 4G memory space. It also includes support of Windows XP, Windows Vista (32 bit), and Windows 7 (32 bit and 64 bit), as well as Linux (Red Hat Enterprise Linux and Novell SUSE).

Other Lattice design tools are available for download separately, including LatticeMico32 Systemand ispLEVER Classic, as well as the PAC Designer tools that target programmable mixed signal design. A Lattice Diamond license will also enable any of those tools that are under license control.

Lattice is continuing to provide access to third party tools with Synopsys’ Synplify Pro advanced FPGA synthesis included for all operating systems supported, while Aldec’s Active-HDL Lattice Edition II simulator is included for Windows.

In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 FPGA family.

Diamond software is available for download from the Lattice website for both Windows and Linux and can be used with either the Diamond free license or the Diamond subscription license.

The Diamond free license can be immediately generated upon request from the Lattice website and provides access to many popular Lattice devices such as the MachXO PLD family, the LatticeXP2 FPGA family and the LatticeECP2 FPGA family at no cost. The Diamond free license also enables Synopsys Synplify Pro for Lattice synthesis and Aldec Lattice Web Edition II simulation software.

The Diamond subscription license that can be purchased adds support for all Lattice FPGAs, including the latest LatticeECP3 devices. It enables Synopsys Synplify Pro for Lattice synthesis and the Aldec Lattice Edition II mixed language simulator for increased capacity and performance.

The Diamond subscription license is $895 per year and enables both the new Diamond software and existing ispLEVER software from a single license. All Lattice ispLEVER software users under active maintenance agreements will receive a Diamond subscription license for no charge that will expire one year from the Lattice Diamond 1.0 release date.

“As designs become larger, and FPGAs are increasingly being used in more cost sensitive, high volume applications, designers need an easy to learn, flexible design environment for exploring different implementations to achieve their cost, power, and performance targets,” said Mike Kendrick, Lattice’s Manager of Software Product Planning.

Video demonstrations of the Lattice Diamond design software can be viewed here.

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