Lattice small footprint FPGA aims for wearables/rich media mobiles -

Lattice small footprint FPGA aims for wearables/rich media mobiles

Claiming it is the industry's smallest and lowest power hardware programmable circuit for consumer mobile and industrial hand-held devices, Lattice Semiconductor this week introduced its ICE40 UltraLite, designed to fit the fast design turn around and time to market needs of mobile and wearable device OEMS.

According to Subra Chandramouli, business development manager for Lattice, the 1.4 by 1.4 mm iCE40 UltraLite is the newest addition to the company's iCE40 Ultra product family (Figure 1 ) targeted mainly at consumer handheld and wearable devices as well as in a range of commercial and industrial apps requiring a variety of interface/bridging, IO expansion, lighting, biometric identification and sensor functions.

Figure 1. Lattice's fourth generation small footprint FPGA targets specific needs of particular portions of the media-rich mobile and wearable markets.

“In the wearable device market in particular, the issue of time to market is a critical one,” he said. “Where time to market in the mainstream of the now maturing mobile phone market is eight months to a year, in wearables it is six to eight months, and even less .”

If it were just a matter of software development, standard microcontrollers would have no problem in this swiftly changing market segment. “But in the wearables portion of the market, everyone in it is trying out not only variations of existing products in various combinations, but new features as well, he said, “and doing so in a market where no one knows yet what will spark the consumer’s interest.”

What the UltraLite offers, said Chandramouli, is the ability to change the hardware configuration to meet the needs of a fast changing market. For example, where the iCE40 Ultra family was targeted at a broad range of mobile and wearable apps, the new UltraLite is even more finely tuned. First of all, he said, there is its size. The 1.4mm x 1.4 mm die and its 42 microwatt standby power consumption are targeted for size constrained, power sensitive and cost-conscious mobile and first generation Android derived wearable devices.

Due in part to a shift to a 40 nanometer CMOS process, other size and power reduction improvements come from the a fewer number of LUTs, but ones specifically targeted at particular applications. Compared to the previous Ultra series with 1100 to 3520 programmable Look Up Tables (LUTs), the UltraLite comes two device densities of 640 or 1K Look Up Tables (LUTs) of logic with programmable I/Os that can be used as an interface port or general purpose I/O. It also has up to 56 Kbits of Block RAM .

The subset of mobiles and wearable apps in consumer and industrial devices that the UltraLite is specifically targeted at, he said, are those which need to perform such functions as infrared (IrDA) protocols, LED servicing, barcode emulation, GPIO expansion, SDIO level shifting that applications such as remote control and pedometers require. Specifically, the UltraLite incorporates RGB PWM IP, with the three 24 mA constant current RGB output and all the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer.

It also has a 400 mA constant current IR driver output that provides a direct interface to external LED for applications requiring Infrared (IrDA) data protocols. He said designers who want to incorporate this into their wearable/mobile design simply implement the modulation logic that meets their needs, and connect the IR driver directly to the LED, without the need of external MOSFET or buffer.

The design also incorporates a 100 mA Barcode Emulation driver output provides a direct interface for applications such as barcode scanning. Much requested by engineers at mobile and wearable companies such as , the chip has additional dedicated logic to allow its 100 mA and 400 mA drivers to also be combined to be used as a 500 mA IR driver.

He said the the shift to a smaller but more targeted LUT array means that chip area is freed upfor still other I/O features customers were asking for such as programmable multiple value pull-up resistors, controllable on a “per-pin” basis.

Lattice is not the only one
Lattice is not the only hardware programmable device market targeting the wearables market, which MarketsAndMarkets estimates to grow to $11.61 billion by the end of 2020 at a compound annual growth rate (CAGR) of 24.56% from 2014 to 2020.

Given that potential other small footprint programmable hardware vendors such as Cypress Semiconductor and its pSOCs and QuickLogic with its ArcticLink are there as well. All three programmable hardware vendors are gambling that they have a mix of capabilities that will appeal to developers of nextgen mobile phones as well as the new wearables markets.

For QuickLogic and its ArcticLink programmble customer specific standard product platform , said Brian Faith, VP of Worldwide Sales and Marketing, it is the company's nonvolatile programmable fabric that allows it to quickly build FPGA-based CSSPs targeted at specific subsets of the mobile and wearable markets. In addition, the company has invested heavily in developing the range of motion sensor and user interface algorithms that wearables – and smartphones – require. The company is also working on a new programming interface that allows developers to program its hardware using the C language, rather than work in hardware languages such as VHDL and Verilog.

According to John Weil, VP of Marketing for PSoCs at Cypress Semiconductor, his company comes to this market with a range of capabilities, in addition to its newest Bluetooth optimized PSoc family designed specifically for the nearbody networking that wearables will require.

First, on the packaging side, in addition to the low profile shrink small outline (SSOP)and Quad Flat No-leads (QFN) packaging, pSoCs can also be fabricated with the company's proprietary wafer-level chip-scale packaging (WLCSP). This, he said, allows developers to take a design to production in a package/die area of no more than 6.9 square millimeters, about two to three times smaller than what is achieved with SSOP and QFN.

Second, Weil said, is its PSoC Creator Integrated hardware and software development environment that allows even novice developers to quickly do a hardware and software design with minimal knowlegdge of C and none at all about FPGA programming tools such as Verilog and VHDL.

The third thing it brings to the table, he said, is that the programmable fabric in its pSoCs handles not only the digital portion of a design but incorporates the many analog functions that most wearable designs require. “Most other approaches, FPGA or MCU based, stll require a lot of external circuitry for these needed analog functions,” he said..

“I have seen all sorts of market estimates for the wearables market,” said Weil, “and the safest estimate you can make is to assume that it is going to be huge.” He said what is making it difficult to come up with really accurate estimates is the skew introduced by the fact that there are usually several generations of devices on the market at the same time all competing for the consumer's attention and all requiring the fast turnaround from design to product in four to eight months.

Not even the more mature smartphone market is immune to this fast turn around requirement even though a typical time frame is about eight months to a year. But often, said QuickLogic's Faith, mobile developers at the larger companies may be evaluating three or four alternate hardware and software solutions for use in next generation design, each with its own set of hardware and software differences and design turnaround requirements.

“Traditional designs based on microcontrollers just do not give them the flexibility to change gears quickly as far as hardware configuration is concerned when they have pinned down a final design,” said Lattice's Chandramouli. “Small footprint programmable devices are the only way they can get the flexibility and maneuvering room they need.”

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