Going for the sweet spot in applications such as wireless small cell base stations, microservers, broadband networking and video apps, Lattice Semiconductor has taken the wraps off its ECP5 family of dedicated functionality FPGAs which will be available in high volume by August. .
Designed to perform critical functions as a companion chip to ASICs and ASSPs in these markets, the ECP5's architecture www.latticesemi.com/ecp5.incorporates a 100 LUTS (look up table) FPGA into a die size of 7.0 by 6.6 mm and achieves a 40% lower cost than competing solutions.The chip (Figure 1 below ) incorporates up to 88K of LUTs based logic slices with an enhanced routing architecture, as well as dedicated logic for a dual-channel SERDES and digital signal processing functions.
“The global deployment of next generation telecommunications systems is driving small-cells into high-volume, access and networking equipment is becoming commoditized and video display technologies continue to advance,” said Lattice Semiconductor President and CEO Darin Billerbec.
“For each of these applications, FPGA capabilities in a tiny, low-cost form-factor burning just milli-watts of power can eliminate many roadblocks for pursuing opportunities that would otherwise be ruled out due to ASIC development costs and schedules, or ASSP inflexibility and availability.”
When configured for use in wireless and wireline applications, the ECP5 can be used data path bridging and interfacing in a small, low-cost 10 x 10 mm copper pillar flip chip (Figure 2 below ) package that allows it to be used in . outdoor small-cells, at extremely low-cost. He said they can also be used in smart SFP (small form-factor pluggable) transceiver applications for broadband access equipment, including integrated operation and maintenance..
Outside of communications, he said, the company is targeting the ECP5 devices for use in low power PCI Express side-band connectivity for microservers. For industrial video cameras, ECP5 FPGAs can implement the entire image processing functionality in a device that consumes under 2W.Smart ball depopulation further simplifies package integration with existing PCB technology and reducing overall system cost.
Claiming 30% lower total power than other FPGA devices, he said this has been achieved by means of architectural enhancements that allow stand-by mode operation of the individual blocks including SERDES, dynamic IO bank controllers and by the use of reduced operating voltages.
“This enables single channel 3.25Gpbs SERDES functions starting below 0.25W, ” said Bellerbec, “and quad channel SERDES functions starting below 0.5W for supporting a broad range of interface standards, including DDR3, LPDDR3, XGMII and 7:1 LVDS, PCI Express, Ethernet (XAUI, GbE, SGMII) and CPRI.”
The ECP5 FPGA family is supported today in the the company's Diamond Software tool package..