Version 1.4 of Lattice Semiconductor Corp.'s ispLEVER Classic design tool suite includes Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH 4000ZE CPLD fitter with improved power optimization. ispLEVER Classic is the design environment for Lattice CPLDs and mature programmable products.
Synplify Pro HDL Analyst provides a way to visualize high-level register transfer level (RTL) Verilog or VHDL. It allows cross-probing between the graphical diagrams and source code to ensure that the coding style they use is the most efficient for the target CPLD. For example finite state machines (FSM) are automatically extracted by HDL Analyst and displayed graphically as a bubble diagram with state transition arrows and a table of state encodings.
The Classic 1.4 fitter now automatically enables the ispMACH 4000ZE CPLDs Power Guard feature for unused I/O and clock resources to avoid unnecessary internal switching. It also includes improved features and educational material for the popular ispMACH 4000 CPLD family. The synthesis interface to the 4000 family has been upgraded with additional optimization control and a means to reference a Synplify Design Constraints (SDC) file for timing objectives.
Online Help now includes links to key technical 'How To' topics for ispMACH 4000 architectural features and power estimation. A new generic schematic library manual describes logic symbols that are portable across SPLD and CPLD device families. The Classic 1.4 design software is bundled with the ispVM System 17.8 programming environment.
The ispLEVER Classic 1.4 tool suite for Windows is available immediately for free and is compatible with Windows XP/Vista/7 and operates as a 32-bit application.