In the last 25 years, the internal peripherals found in microcontrollers (MCUs) have changed drastically. Originally, many MCUs contained only RAM, ROM, and — maybe — a rudimentary timer. As MCUs have progressed, additional peripherals have been incorporated in devices costing around a dollar or less. Timer/Counters, PWMs, and standard serial interfaces such as UARTs, SPI, and I2C are commonplace in these inexpensive microcontrollers. The other big change is that 32-bit CPUs are replacing 8-bit devices in the same price range.
However, even with these feature rich, inexpensive microcontrollers, there will always be project specific hardware interfaces or new third-party interfaces that the microcontroller venders cannot quickly support. Often, this requires designers to use external hardware or to implement the interface in firmware by “bit-banging.” The bit-banging approach uses firmware to toggle an input/output (I/O) port, usually to implement a serial interface. I also refer to it when I have to monitor a port to decode serial data as well. Using either external hardware or bit-banging to implement an interface adds cost to a design. The cost of additional external hardware is obvious, but using software to implement a serial interface may also require a faster, and therefore more expensive, CPU.
Most common MCUs today support SPI, UART, and I2C interfaces, but there are still many times where some internal user programmable logic can come in very useful. Several companies — including Atmel, Cypress, Microchip, and NXP — have added some user-definable logic to their parts to address some of these problems. These devices are mainly MCUs with added logic. The CPU is still the main workhorse and the added logic is used to make the CPU more efficient. These device types are usually found in cost-sensitive products, but are also used as small co-processors to assist in low-level tasks to offload the main processor for greater efficiency.
FPGAs, on the other hand, have been moving toward a similar target but from the other direction. Xilinx and Altera have been adding hard and soft core processors for many years to create System-on-Chip (SoC) devices. The FPGA approach is usually more expensive, but when a project requires significant custom logic, they can be a cost-effective approach. These devices are invaluable for prototyping ASICs, implementing low volume products where time to market is key, and creating larger products that require ongoing hardware flexibility.
Both of these device types — MCUs with logic and FPGAs with CPUs — provide hardware flexibility in the field. Once Flash-based devices became common, field upgrades became the norm. At first the designer had the ability to upgrade just firmware, but now, both hardware (logic) and firmware can easily upgraded in the field. Devices from computer mice to high-speed network routers can be field-upgradable with the ability to reprogram both the firmware and hardware in a single device.
The four companies mentioned earlier (Atmel, Cypress, Microchip, and NXP) have all provided custom “Glue” logic to help offload the main processor or to eliminate the need for external logic. Each company has taken a different approach in both the kind of logic blocks provided and the ways in which they are interconnected to each other and to other on-chip entities such as timers, UARTs, and I/O pins.
In order to make the best decision as to what will work best for your project, it is important to understand how each of these venders has implemented the internal programmable logic. Just a simple internal AND or OR gate may be sufficient to eliminate an external component or to improve CPU performance. All four methods allow input and output signals to be gated by the custom logic. This can be used to gate an input with a clock so that a counter can be used to measure an external clock frequency. One simple example supported by each of the four types of logic blocks is a way to modulate the output of a UART to be used for IR communication. It's not just the fact there is an internal AND gate as show in Figure 1, but the ability to route the signals from a clock or counter and the UART TX output to the AND gate.