LONDON RF Engines has released a library containing more than sixty Fast Fourier Transform (FFT) cores for use in Xilinx FPGA devices. The RF Engines (Isle of Wight, U.K.) library is supplied on a single CD, and includes FPGA netlists for a range of FFTs that cover different target devices, transform lengths and sample rates.
Cores are provided for Xilinx Spartan III, Virtex II, Virtex II Pro and Virtex 4 FPGA devices, with FFT transform lengths ranging from 32 points, up to 32K points for some device types.
Each core can be configured to compute the inverse FFT function, and includes a bit reversal function to allow frequency data to be output in natural order. RFEL says that compared to existing FFT generation tools, the FFT library provides options for higher real-time processing speeds, and more silicon efficient options for lower speed requirements. The library also differs from other solutions in the level of support provided to the integrator. Each design includes a bit-true PC simulation, a customised data sheet, and a test bench for the core. Furthermore, the product also includes telephone or email support for integration assistance and advice. The designs use pipelining techniques that permit the core to run in continuous real-time (streaming I/O) at high sample rates, and two architectures have been used to allow designers to make a trade-off between sample rate and silicon resource usage.
The HiSpeed architecture has been used to produce the most silicon efficient cores in the library, and supports complex sample rates up to around 100 MS/s depending on the device type and transform length, whilst cores based on the QuadSpeed architecture support complex sample rates up to 500MS/s in some cases. RF Engines has used fixed-point arithmetic techniques in order to grow the precision of the data as it progresses through the transform. Thus, for example, a 14-bit integer input grows to around 23-bits by the time it reaches the output of a 32K transform. 'Growing' the data in this way ensures that the precision is maintained, whilst use of FPGA resources is kept to a minimum. This approach is markedly different to other available solutions, which use a fixed bit-width from input to output, and often require the designer to sacrifice precision in order to save silicon. Each core in the library is supplied as an EDIF netlist, and is supplemented with a bit-true Matlab model, a custom data sheet, and a VHDL test bench. The library is supplied with a site-wide licence that permits use for R&D purposes and allows the cores to be shipped in manufactured products.