Low power IP technology gains funding - Embedded.com

Low power IP technology gains funding

CAMBRIDGE, England — Low power IP developer Adiabatic Logic has received a £500,000 Exceptional Research and Development Grant from the UK Department of Trade and Industry (DTI).

Awarded for projects that will lead to technological developments of strategic importance for a technology or industrial sector, the grant will enable Adiabatic Logic to accelerate the development of its patented Intelligent Output Driver (IOD), which aims to deliver a 50-75% dynamic power savings in chip I/O for portable devices such as laptops, smartphones, handheld computers, digital cameras and MP3 players.

Adiabatic Logic is now looking to close its first funding round, which, coupled with the DTI funding, will enable it to produce 130nm technology-specific, production-worthy IP cells and a design kit compatible with electronic design automation (EDA) tools. The company will also use the capital to develop at least two credible reference design wins to prove IOD delivers the power savings in leading-edge silicon.

Simon Payne, CEO of Adiabatic Logic, said: “We are delighted that the DTI has awarded us this grant which we view as a major endorsement of our technology and our business plan. In electronics design, power is the next frontier to be conquered and our technology has huge potential to deliver significant power savings.”

Adiabatic Logic’s IOD IP cell is designed to replace the conventional pad drivers in an integrated circuit (IC) and uses a patented energy recycling technique which exploits the principle of adiabatic – or reversible – computing. IOD recycles energy normally wasted each time a digital I/O pad driver makes a switching transition.

As well as power saving, IOD technology can also reduce the overall component count and bill of material cost by minimising battery size, cutting DC-DC converter/thermal management costs and eliminating the requirement for terminating resistors.

The first silicon implementation of IOD was completed in October 2003 using a 0.6-micron process technology. The results showed power savings of more than 50 per cent compared with traditional I/O schemes. Earlier this year, Adiabatic Logic signed a co-operation agreement with IMEC, Europe’s independent microelectronics and nanotechnology research center, which will result in IOD being incorporated into IMEC’s library of radiation hardened 180nm technology, for use in space, medical and scientific applications.

The IOD technology the speed of submicron CMOS to actively mimic the voltage-current drive characteristics of a classic driver with a source (or series) terminator resistor. It does this in such a way that the bulk of the current is delivered to the load capacitance non-resistively from a reservoir capacitance maintained at a mid rail voltage, assisted by the inherent inductance of the load. The on-chip reservoir capacitance delivers charge on rising edges and recovers charge on falling edges thereby recycling energy, which is conventionally wasted.

Founded in 2002, Adiabatic Logic is part of the Cambridge Technology Group and s based at Dry Drayton, on the outskirts of Cambridge.

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