Low Power or High Performance: A Tradeoff Whose Time Has Come? - Embedded.com

Low Power or High Performance: A Tradeoff Whose Time Has Come?

The desire to operate unattended for long periods of time has been a driving force in designing wireless sensor networks (WSNs) over the past decade. By focusing primarily on this requirement, platform designers have usually sought out those hardware com- ponents with the lowest sleep and active power draws.

Modern platforms, for example, use low-power microcontrollers (MCUs) like the Atmel ATmega128 and TI MSP430. These devices draw mW of power while active and µW when sleep- ing, trading off low power for limited memory and slower clock frequencies. In turn, the limited processing and memory resources of these platforms restrict the applications they can support.

Typical applications follow a sense-store-send-sleep archetype where on-board sensors are infrequently sampled and measurements are delivered to gateways over single- or multi-hop paths. Unfortunately, computationally intensive and higher-data-rate applications are not well supported on these platforms.

Applications that involve high-performance or high-resolution signal processing, such as structural monitoring, habitat monitoring, and motion analysis, typically have to make compromises to work around platform limitations. These applications tend to be characterized by alternating intervals of intense activity followed by periods of relative inactivity.

In traditional deployments, designers are forced to make compromises related to the type of processing that nodes can perform, the responsive- ness of the overall system, and in the placement of communications and computation elements] within the system. The only alternative is to use platforms that sacrifice power for processing speed, or platforms that combine low-power MCUs with either high-performance but energy-hungry CPUs or analog processing.

In this paper, we examine whether modern 32-bit processors can rival their 8/16-bit counterparts in terms of both power and performance. We explore this question in the context of today’s leading 32-bit embedded architecture – the ARM Cortex-M3 MCU – and find quite substantial progress when compared with a leading 16-bit embedded architecture – the TI MSP430 MCU [37].

We ground our study in two new WSN platforms based on the ARM Cortex-M3: Egs and Opal. Both platforms use the Atmel SAM3U variant of the Cortex-M3 because of its low-power states, fast wakeup support, and integrated memory protection]. Egs targets wireless health applications while Opal targets robust environmental monitoring. Both target applications demand higher performance than motes based on 16-bit MCU provide but also require lower energy consumption than conventional 32-bit systems.

Our results show that Cortex-M3-based platforms can offer significantly better per-formance and power profiles for next-generation WSN applications with a reasonable increase in power draw for traditional sense-store-and-sleep applications.

Applications with heavy workload requirements benefit from an order-of-magnitude faster process- ing, with the potential for further speedups when frequency scaling is used. Additionally, the Cortex-M3 provides a serial interface that does not limit the end-to-end throughput of the network.

These platforms also achieve good code density due to the efficient ARM Thumb-2 instruction set, but require between 1.1 and 3 times greater RAM space, which in turn slightly increases current draw during sleep. In terms of power, the higher-powered sleep mode on the Cortex-M3 only translates to a about a two fold greater whole-system power draw while running a typical workload for sense-store-send-sleep-style applications under TinyOS.

These results show that the dichotomy of low power or high performance is, for many WSN applications, now a nearly false one. Freed from the limitations of 16-bit operation, system developers can now focus on higher-performance signal processing, sensor-hosted databases, and spec-compatible JVMs instead of how to squeeze the last byte or cycle out of their 16-bit program.

These results suggest that while 32-bit processors are not yet ready for applications with very tight power requirements, they are poised for adoption everywhere else. Moore’s Law may yet prevail.

To read this external content in full, download the complete paper from the online archives at Alexander University Erlangen. 

*** Other authors of the paper are Christian Richter, Branislav Kusy, and Michael Bruenig, Australian Commonwealth Scientific and Research Organization; Wanja Hofer, Alexander University Erlangen, Nuremberg, Germany; Thomas Schmid, University of Utah; Qiang Wang, Harbin Institute of Technology, Germany; Prabal Dutta, University of Michigan; and Andreas Terzis, Johns Hopkins University.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.