Low-power PHY IP fits PCI Express, XAUI, and SATA - Embedded.com

Low-power PHY IP fits PCI Express, XAUI, and SATA


Synopsys has expanded its DesignWare Mixed-Signal intellectual property (MSIP) portfolio with low-power PCI Express, XAUI, and SATA physical layers (PHYs) in the 130- and 90-nm processes. These mixed-signal PHYs offer differentiated, advanced built-in diagnostics for evaluating link performance and margin.

The benefits provided by the PHYs include compliance to the relevant standards, low jitter, and high receive sensitivity, resulting in a lower system bit error rate (BER) and a design that maximizes margin and minimizes power. According to the company, the solutions require only 30% to 50% of the power consumption per lane of present solutions.

The DesignWare SATA and XAUI PHYs are currently available in limited production for 130- and 90-nm process technologies. The PHY for PCI Express is available now for volume production. For more information, visit www.synopsys.com/designware.

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