Low power vs high performance in 8/16 and 32-bit MCUs - Embedded.com

Low power vs high performance in 8/16 and 32-bit MCUs

The desire to operate unattended for long periods of time has been a driving force in designing wireless sensor networks (WSNs) over the past decade. By focusing primarily on this requirement, platform designers have usually sought out those hardware components with the lowest sleep and active power draws.

Modern platforms, for example, use low-power microcontrollers (MCUs) like the Atmel ATmega128 and TI MSP430. These devices draw mW of power while active and µW when sleeping, trading off low power for limited memory and slower clock frequencies.

In turn, the limited processing and memory resources of these platforms restrict the applications they can support. Typical applications follow a sense-store-send-sleep archetype where on-board sensors are infrequently sampled and measurements are delivered to gateways over single- or multi-hop paths. Unfortunately, computationally intensive and higher-data-rate applications are not well supported on these platforms.

This paper examines whether modern 32-bit processors can rival their 8/16- bit counterparts in terms of both power and performance. We explore this question in the context of today’s leading 32-bit embedded architecture – the ARM Cortex-M3 MCU  – and find quite substantial progress when compared with a leading 16-bit embedded architecture – the TI MSP430 MCU.

Some have argued that the dichotomy between high-performance operation and low resource utilization is false – an artifact that will soon succumb to Moore’s Law and careful engineering.

If such claims prove to be true, then the traditional 8/16- vs. 32-bit power-performance tradeoffs become irrelevant, at least for some low-power embedded systems.

We explore the veracity of this thesis using the 32-bit ARM Cortex-M3 microprocessor and find quite substantial progress but not deliverance. The Cortex-M3, compared to 8/16-bit microcontrollers, reduces latency and energy consumption for computationally intensive tasks as well as achieves near parity on code density.

However, it still incurs about a 2X overhead in power draw for “traditional” sense-store-send-sleep applications.

(To read this external content in full, download the pape r from the author archives. )

**Coauthors of this paper also included Kevin Klues University of California, Berkeley; Christian Richter, Branislav Kusy, Michael Bruenig, CSIRO; Wanja Hofer, Friedrich–Alexander University Erlangen–Nuremberg; Thomas Schmid, University of Utah; Qiang Wang, Harbin Institute of Technology and Prabal Dutta, University of Michigan.

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