No matter whether it is design based on an 8-bit or 16-bit MCU, a 32-bit ARM or Atom, or a multicore SoC, one common challenge faces the embedded system developer: as a system's functional requirements and the size of the software grow, it becomes more difficult to ensure that time-critical operations are performed with as little interruption as possible.
The problems can be addressed by either using a faster processor – which is not realistic in many resource-constrained designs – or more commonly execute them in a prioritized manner, through the use of a variety of interrupt management and scheduling schemes.
But this is not achieved easily, as the designer is faced with a variety of roadblocks. Because software cannot predict when interrupts will occur and thus pause execution of other operations, it is no surprise that without a considerable degree of effort, the result is the inability to perform system and application critical operations within the design constraints originally defined.
On Embedded.com are collected a range of design articles, white papers, and webinars as well as columns by Jack Ganssle, Jack Crenshaw and Dan Saks to help you sort through the problems and their possible solutions, including:
And in addition to “Improve Cortex M4 MCU interrupt responses with an Intelligent Peripheral Event System ,” by Andreas Eieland, and Espen Krangnes, and “Interrupts short and simple , ” a three part series of tutorials by Priyadeep Kaur, my Editor’s Top Picks are:
Optimized interrupt handling
Testing the Interrupt Priority Levels of a Microprocessor
Introduction to interrupt debugging
Several recent conference proceedings and journal papers that I found interesting, include:
Embedded.com Site Editor Bernard Cole is also editor of the twice-a-week Embedded.com newsletters as well as a partner in the TechRite Associates editorial services consultancy. He welcomes your feedback. Send an email to , or call 928-525-9087.