LPDDR5 DRAM ready for Level 5 autonomy - Embedded.com

LPDDR5 DRAM ready for Level 5 autonomy


Micron announced that its LPDDR5 memory is now ASIL D certified under ISO 26262, which is considered one of the most stringent safety integrity levels for automotive safety.

The journey to Level 5 autonomy is taking longer than initially expected, but Micron Technology is opting to be well prepared so that any memory content meets tomorrow’s reliability requirements today.

Micron announced that its LPDDR5 memory is now Automotive Safety Integrity Level (ASIL) D certified, under ISO 26262, which is considered one of the most stringent safety integrity levels for automotive safety.

In an interview with EE Times, Robert Bielby, senior director of Automotive Systems Architecture and Segment Marketing at Micron, said the ISO 26262 standard does not explicitly require memory to be ASIL-compliant today, but that it made sense to attain the certification as memory becomes increasingly critical to automotive safety applications.

“We recognized probably three, four years ago that the industry is going to need to take a different view of memory in the context of functional safety.”

He said this industry-first certification combined with Micron’s architecture for its proprietary on-chip safety features will significantly minimize the need for automakers to build in additional mechanisms to mitigate risk as well as allow them to simplify their system design and get to market faster. Functional safety and reliability in harsh environments are key requirements for automotive electronics.

Robert Bielby (Source: Micron Technology)

The ISO 26262 certification also recognizes the changing role of memory and storage in the modern automobile, even those that aren’t fully autonomous, Bielby explained.

“Memory and storage have moved from being in the back seat of the car to being in the front seat,” Bielby said. Data has become even more mission critical for driving today’s vehicles, not just supporting infotainment systems, he added. “Any errors in the system can have a profound impact on the operation of the vehicle.”

Micron has been collaborating with Exida, a product certification and knowledge company specializing in automation system safety, on its automotive memory certifications. As a Class 3 device, DRAM is proving to be complicated when it comes to managing functional safety, Bielby said, which includes system fault coverage that requires manufacturers to design for a certain set of specifications.

Micron has designed its DDR5 DRAM to be compliant with ASIL D, which is most stringent. “We understand the modes at which memory can fail. We put hooks in our product to be able to detect when that memory is not behaving the way it should be behaving.”

Micron’s LPDDR5 DRAM (Source: Micron Technology)

This understanding allows Micron to reduce the need for the overhead that comes with Error Correction Code (ECC), Bielby said. “You’ve got a part which is designed to the best-in-class standard, and we can detect ourselves when things are not behaving properly.”

Eliminating this overhead also allows for performance improvements, he added, because by not requiring the designer to encapsulate everything with ECC, a great deal of compute performance can be recovered, which frees up an SoC to execute more AI calculations.

As it stands now, most vehicles are only hitting Level 3 autonomy, Bielby said, but even today’s anti-lock braking systems have become memory-dependent because there’s electronics components involved and a dashboard indicator that’s dependent on reliable data.

“As you start to get closer and closer to something that really controls the vehicle, this is becoming an essential technology.”

Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.

>> This article was originally published on our sister site, EE Times.

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