The memory specifications game often boils down to getting more performance while keeping power consumption low. This is particular true for Low Power Double Data Rate (LPDDR) DRAM but uses cases such as artificial intelligence (AI), edge computing and 5G are adding to the pressure.
The latest update to the LPDDR5 standard released by the JEDEC Solid State Technology Association, JESD209-5B, increases speeds by 33% to 8533 Mbps as part of a focus to improve performance, power, and flexibility, said Hung Vuong, who chairs JEDEC’s JC-42.6 subcommittee on low power memories . The faster memory speed and efficiency of the latest iteration is aimed at 5G smartphones as well as high resolution augmented reality/virtual reality and edge computing using AI. He said the uses cases beyond mobile devices demonstrate the value of providing the right performance at a lower power.
That includes more data being processed at the edge instead of being sent to a central cloud data center. “The whole architecture of the system is changing,” said Vuong. Both the mobile device and the computing at the edge require more memory without dramatically increasing power consumption because there’s a wireless access point with more computing capability in lieu of sending everything back to the cloud.
Regardless of the use case, pushing up the memory speed has an impact on signal integrity, so the JESD209-5B update includes signal Integrity improvements with TX/RX equalization. The environments of the various LPDDR use cases also create challenges for signal integrity, too. “It is definitely dependent on the use case,” said Vuong. For a smartphone, it’s more manageable, but it becomes more challenging with automotive or edge computing. “It will become tougher for them to reach 8.5 gigabit. They might have to operate at a little bit lower performance, but that’s design dependent,” he said. “We have some mechanism there for them to take advantage and hopefully it meets their need.”
Some of the use cases, such as automotive , put a high priority on reliability, so another key feature of the JESD209-5B update is the Adaptive Refresh Management feature, which helps the memory device adjust in more stressful operating environments, including more extreme temperatures. “With the adaptive refreshed management, what we’ve defined is a mechanism to define a reliability level,” said Vuong. The feature enables the host or the software can set some level of reliability that they expect from the device and meet data reliability expectations. “If you are in the extreme operating condition, you might adjust the reliability level a little bit higher so that you won’t lose as many bits.” In a phone or other non-critical environment, that reliability can be lower, he said.
Micron is one company that’s aimed to meet the specific reliability requirements of automotive with its LPDDR5 memory. Earlier this year the company began sampling LPDDR5 memory that is hardware-evaluated to meet the most stringent Automotive Safety Integrity Level (ASIL), ASIL D. Its LPDDR5 memory is part of a new portfolio of memory and storage products designed for use in different ADAS technologies that might use functional safety-evaluated DRAM, including automatic emergency braking systems, lane departure warning, adaptive cruise control, and blind spot detection systems. All require extremely low latency and reliability, even in a vehicle that’s not fully autonomous. ASIL is a risk classification scheme defined by ISO 26262, and as more electronic devices are integrated into vehicle to enable systems that take great control of vehicles, complying with the spectrum of ASIL classification has become a more frequent requirement.
The updates to LPDRR5 reflect the continuous demand for memory bandwidth regardless of use cases—there’s more data to process, and more compression necessary for applications such as graphics and gaming, said Vuong. “It’s not going to stop with 5G or AI.” Two years from now the data rate will have to be increased again. “But at 8.5 gigabit per second, sooner or later, we’re going to run into a Moore’s Law and hit the wall, and we have to figure out how to move that data.”
The first iteration of LPDDR5 was released in the first half of 2019, operating at an input/output (I/O) rate of 6400 MT/s, 50 per cent higher than that of the first version of LPDDR4, which came in at 3200 MT/s when it was published in 2014. The LPDDR5 architecture redesign included a move to a 16-banks, programmable, multi-clocking architecture, and introduced two new command-based operations to improve system power consumption by reducing data transmission.
Samsung was quick out of the gate with mass production of its 12-Gb LPDDR5 mobile DRAM as the new standard was published, only months after announcing mass production of its 12-GB LPDDR4X, targeting 5G-capable premium smartphones that run artificial intelligence (AI) applications. As part of a 12-GB package, Samsung’s LPDDR5 touted data transfers of 44 GB of data (the equivalent of 12 full-HD movies) in a second, while reducing power consumption by 30%.
>> This article was originally published on our sister site, EE Times.
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