Micron Technology’s latest memory technology aimed at smartphones offers a potential triple threat when it comes to reducing power consumption, making it more likely that DRAM will proliferate at the edge.
Micron recently announced that its low-power DDR5X (LPDDR5X) DRAM has been validated for MediaTek’s new Dimensity X1 5G chipset for smartphones, representing the flagship of MediaTek’s Dimensity 5G SoC portfolio. Micron has already shipped samples of its LPDDR5X built on its 1α (1-alpha) node aimed at high-end smartphones.
As the name implies, LPDDR5 is already power conscious. The July release by JEDEC of its LPDDR5X extension further conserves power while offering higher bandwidth and memory speed for enhanced 5G communication.
Micron’s validated samples support data rates up to 7.5 Gb/s, and the company anticipates future samples will support data rates up to 8.533 Gb/s. That’s 33 percent faster than previous generations of LPDDR5.
Chris Moore, marketing vice president for Micron’s mobile business unit, noted in an interview that the 1α node further reduces power consumption. “You’re going to get some natural power savings moving to 1α.” With faster data transfers between the application processor, the processor can revert to low-power mode faster since data delivered from memory is accelerated.
That’s beneficial for battery life, Moore said. “We all want the day when our phones last a week or two without actually having to plug it in. I don’t know if we’re going ever get there because we keep enhancing all the features in the phone as well.”
LPDDR5’s key enhancement for smartphones is allowing users to multitask as they would on a PC. That functionality includes the ability to open multiple apps on a phone display simultaneously along with drag-and-drop and cut-and-paste across apps. Those functions are now available with new foldable phones.
Moore said the LPDDR5X power profile and performance capabilities enable multitasking, making this DRAM version more ubiquitous beyond smartphones as AI becomes more widespread. Already, some laptops are moving to LPDDR since users want longer battery life.
“There [are] quite a few laptops out there today using [low power] and they’re going to move to LP and LP5X. That’s a natural progression,” he said. “They may even have more need for that speed and power than a handset will [in the] short-term.”
Eventually, Moore said LPDDR5X will find its way into automotive applications, improving the necessary responsiveness required to communicate over 5G for quick inference. “There’s going to be more and more storage and memory in cars moving forward,” he predicted.
Power consumption is also important in automotive applications since it places additional strain on batteries. Earlier this year, Micron began sampling LPDDR5 memory that is hardware-evaluated to meet the stringent Automotive Safety Integrity Level (ASIL) spec. That introduction is part of a new portfolio of memory and storage products designed for deployment in different ADAS technologies that might use functional safety-evaluated DRAM, including automatic emergency braking systems, lane departure warning, adaptive cruise control and blind-spot detection systems.
DRAM’s ability to scale may also allow LPDRR5 to find its way into edge devices. “The future of DRAM itself is very strong,” said Moore. “You’re going see highly specialized compute and highly specialized memory that are customized for whatever that edge device needs.”
The edge is also expected to be very cost sensitive given the projected deployments of billions of devices, he added.
Micron’s LPDDR5X focus on the smartphone ecosystem follows its introduction of LPDDR5, the 1α-based LPDDR4X, 176-layer NAND-based UFS 3.1 and uMCP5 devices, giving the chipmaker a first-mover advantage after trailing in DRAM and NAND flash advancements.
Last year, Micron touted its use of replacement-gate technology for its latest 3D NAND flash memory for 176-layer NAND, shipping in volume as other players were still focused on 128-layer NAND. In early 2021, Micron unveiled its 1α-node DRAM, offering what it claimed is a 40-percent improvement in memory density over its 1z-node DRAM, as well as a 15-percent boost in power-savings for mobile devices.
The first iteration for LPDDR5 included significant jump in I/O rate compared to the initial version of LPDDR4, marking an architecture shift. The redesign of LPDDR5 included a move to a 16-banks, programmable, multi-clocking architecture. It also introduced two new command-based operations to improve system power consumption by reducing data transmission.
>> This article was originally published on our sister site, EE Times.
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