LSI processor inspects packets at 10 Gbits/s - Embedded.com

LSI processor inspects packets at 10 Gbits/s

SAN JOSE, Calif. — LSI Corp. has announced a single-chip processor that can handle deep packet inspection at rates of up to 10 Gbits/second. The company hopes to stake out a position in the strategic area of responding to the needs of applications as they run over high speed networks.

The T2000 aims to tackle pattern matching jobs such as searching for evidence of a virus, spam or a network intrusion in security systems. The company cites market reports suggesting more than 80,000 such systems sold in 2006 alone.

The chip is the latest from former startup Tarari that has helped pioneer the area known as content processing. LSI acquired Tarari in September 2007 as part of a push deeper into communications for the company long known for storage chips.

Networking silicon “is an area of development and we are working on making it a bigger part of our business,” said LSI chief executive Ahbi Talwalkar in a May interview.

Bob Wheeler, principal analyst with The Linley Group (Mountain View, Calif.), said content processing at 10 Gbit/s rates is a significant milestone. However, NetLogic has talked about plans for a similar part, and the LSI chip will not be in production until early next year.

“It's a horse race to see who gets there first,” Wheeler said.

Both companies are now targeting the PCI Express interface. The T2000 uses eight 2.5 GHz Express links. NetLogic rolled out an early product for the HyperTransport interconnect, but the bus has failed to much traction in communications, driving NetLogic toward Express.

Tarari originally said it would deliver a HyperTransport version of its chip, but it's unclear when or if it will come to market. “The interest in a HyperTransport version is not as great as when we first put it on our roadmap,” said Bob Lutz, a product line manager at LSI.

The T2000 lacks logic for accelerating XML traffic, something Tarari's existing processors sport. Wheeler said the XML feature is used by a separate set of customers, and LSI probably chose to leave it out to reduce cost, power and time-to-market for the new chip.

Deep packet inspection is seen as an important next step for networking systems. However, it is being implemented variously in host software, coprocessors ASICs and FPGAs.

Freescale integrated content processing capabilities running at 2.4 Gbits/s from its Seaway acquisition into its MPC8572 dual-core PowerPC, as well as a part that Freescale claims runs at 10 Gbits/s. Cavium Networks uses a simplified deep packed inspection engine in its Octeon chip.

“This is an emerging market in which Tarari is a leader, but the market is fragmented over which approach to take,” said Wheeler. “The question is when to integrate.”

He said he expects LSI ultimately will integrate the Tarari features into the gateway processors it acquired from Agere Systems. The company launched an alliance to shepherd the market for such chips earlier this year.

The T2000 can address up to 4 Gbytes of DDR2 main memory where a host processor queues up pattern matching jobs. The chip uses hard-coded state machines to make the comparisons, tapping up to one million user-generated matching rules.

The chip is sampling now and sells in quantity for prices ranging from $200 to $300 for throughput speeds that start at 2.5 Gbits/s.

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