Using technology licensed from ARM Ltd., LSI Corp. has successfully developed an ARM-based network processor SoC capable of linking up to 16 cores. First chip’s using the technology will be announced next February.
LSI’s Axxia processor is using a new on-chip interconnect licensesd from ARM, called the Corelink CCN-504, which is capable of delivering interchip throughput of about a terabit/second.
While the initial version of the CoreLink interconnect handles up to 16 cores, there are plans to extend that to 32 cores in the future. It is to be used by LSI in the Axxia to link a number of CortexA15 cores it has licensed from ARM as well as its own DSP and accelerator blocks.
The intercconect makes use of a ring topology although the architecture also allows configuration as a mesh or crossbar as well, allowing it to scale far beyond ARM implementations based on the current AMBA bus, which is limited to 8 cores.
The coherent link supports quality of service to the cores as well as to on-chip level 3 cache and DDR memory. LSI plans to use it for both standard products and as part of its ASIC service.