Texas Instruments' SN65LVDS822 LVDS receiver IC supports a 4-MHz pixel clock in printers, copiers, digital cameras, fuel pump displays and appliances with small LCD panels. Compared to competitive devices, the SN65LVDS822 FlatLink LVDS receiver accepts a lower pixel clock, enabling 30 percent longer video transmission distance, with 60 percent fewer wires to reduce electromagnetic interference (EMI) and power consumption.
- Supports wide pixel clock range: Receives a low pixel clock from 4 MHz to 54 MHz to enable panel resolutions of 160 by 120 (QQVGA) to 1024 by 600 (WUXGA) at 60 frames per second (fps) with 24 bit-per-pixel (bpp) color that until now required parallel LVTTL/LVCMOS interfaces.
- Reduced wire count: Supports both 4:27 and 2:27 deserialization, providing the flexibility to further reduce wire count. The 2:27 mode with 14x sampling enables a 40 percent lane count reduction to two data lanes for systems with tight space constraints.
- Flexible PCB layout and low EMI: Bus swap feature and reduced LVDS swing offer engineers greater board design flexibility, while the 3-way selectable CMOS slew rate control reduces EMI by matching the slew rate with the needs of the application.
- LVCMOS output: Supports 1.8-V to 3.3-V CMOS signals to meet a wide range of LCD panel requirements.
Combining the SN65LVDS822 receiver with the SN75LVDS83B LVDS transmitter forms a complete bridge interface between a system’s LCD panel and video processor, such as one of TI’s OMAP and DaVinci processors. The SN65LVDS822 is an extension of TI’s FlatLink serial interface technology, which reduces the number of signal lines used for synchronous parallel data bus structures with no loss in data throughput.
The SN65LVDS822RGZEVM evaluation module can be purchased today for a suggested retail price of US$99. An IBIS model is also available for verifying board signal integrity requirements.