Ball grid array (BGA) device packaging is today’s standard for housing a range of highly advanced and complex semiconductor devices like FPGAs and microprocessors. The technology of BGA packaging for embedded designs is steadily advancing to keep up with chipmaker technical advances, with this type of packaging splintering out into standard and micro BGAs. Today, both types deal with increasing numbers of I/Os, and this means signal escape routing is difficult and challenging, even for experienced printed circuit board (PCB) and embedded designers.
The top job for the embedded designer is to develop appropriate fan-out strategies that won’t adversely affect board fabrication. There are several major considerations involved in selecting the correct fan-out/routing strategy: ball pitch, land diameter, number of I/O pins, via types, pad size, trace width and spacing, and the number of layers required to escape the BGA.
PCB and embedded designers will always be challenged to use the minimum number of board layers. The number of layers needs to be optimized to reduce cost. But sometimes a designer must rely on a certain number, for example, to suppress noise by sandwiching actual routing layers between ground plane layers.
Aside from those design factors inherent in particular BGA-based embedded designs, a major portion of the design involves two basic methods the embedded designer has to perform to correctly escape signal traces from a BGA: dog bone fan-out (Figure 1 ) and via-in-pad (Figure 2 ). Dog bone fan-out is used for BGAs with 0.5 millimeter (mm) and above ball pitch, while via-in-pad is used for BGAs and micro BGAs with below 0.5 mm ball pitch, also known as ultra-fine pitch. Pitch is defined as the spacing between the center of one BGA ball to the center of the next one.
It’s important to know some basic terminology associated with these BGA signal routing techniques. The term “via” is the most prominent. It refers to a pad with a plated hole connecting copper tracks from one PCB layer to other layers. High-density multi-layer boards may have either blind or buried vias, also known as micro-vias. Blind vias are visible only on one surface; buried vias are visible on neither surface.
Dog bone fan-out
Dog bone BGA fan-out provides partitioning into four quadrants with a wider channel in the middle of the BGA to run multiple traces from inside. Several key steps are involved to break out signals from the BGA and connect them to other circuitry.
The first step is to determine the via size needed for the BGA fan-out. Via size depends on a number of factors — device pitch, PCB thickness, and the number of traces to be routed from one area of the via or one perimeter to the next. Figure 3 shows three different perimeters associated with a BGA. A perimeter is the boundary of a polygon is defined in a shape of a rectangle or square surrounding the BGA balls.
Consider an imaginary line going through the first row (horizontally) and first corresponding column (vertically) comprising the first perimeter, and again for the second and third perimeter. A designer starts off routing the outer perimeter of the BGA, then moving inward, and, in the end, toward the inner-most perimeter of the BGA balls. Via size is calculated using land diameter and ball pitch, as shown in Table 1. The land diameter is the diameter of the pad of each BGA ball.
Once the dog-bone fan-out is done and the particular via pad size is determined, step two is to define trace width for traces coming into the board’s internal layers from the BGA. A number of factors go into confirming trace width. Table 1 shows that trace width. Minimum space required between traces define a BGA’s escape routing. It’s important to know that reducing spacing between traces increases board fabrication cost.
The area between two vias is called a channel for running the traces. The channel area between adjacent via pads is the smallest area through which the signal must be routed. The number of traces that can be routed through this area is calculated using Table 1.
As Table 1 shows, performing BGA signal escape routing is defined by trace width and the minimum space required between traces. The channel area between adjacent via pads is the smallest area through which the signal must be routed.
The number of traces that can be routed through this area is calculated using Table 2 .
A number of traces can be routed through various channels. For example, one or two traces can be routed and sometimes three if BGA pitch isn’t very fine. For instance, with a one-millimeter pitch BGA, multiple traces can be routed. However, with today’s advanced PCB designs, most often only a single trace is routed through a channel.
Once the embedded designer has determined trace and space width, the number of traces routed through one channel, and type of via to be used for the BGA layout, he or she can estimate the number of layers that will be required. Use of fewer I/O pins than the maximum can reduce the number of layers. If routing on primary and secondary side is allowed, then the two outer perimeters can be routed without using vias. The next two perimeters can be routed on the bottom side.
At step three, the designer keeps impedance matching as required and determines the number of routing layers to be used to completely breakout the signals from the BGA. Next, he or she routes the BGA’s outer periphery using the top board layer or the same layer where the BGA is placed.
The remaining inner parameters are distributed among internal routing layers. Depending on the number of traces routed internally within each channel, a fair estimate is made on the number of layers required to completely route the BGA.
Once the outer periphery is routed, the next periphery is routed. The set of images in Figure 4a and Figure 4b illustrate how a PCB designer routes different BGA peripheries, starting from the outermost and moving to the center. The first image shows how the first and second inner periphery is routed. Subsequent internal peripheries are similarly routed until the BGA is completely routed.
Figures 4a and 4b: How to route different BGA peripheries, starting from the outer most and moving to the center.
In some designs where electro-magnetic interference (EMI) is a concern, the external layer or top layers aren’t used to route even the outer periphery. In that case the top layer is used for a ground plane. EMI includes the susceptibility of a product to fields from the outside world that couple in and radiate emissions from a product, which causes it to fail compliance tests. A product is considered EMC compliant if it satisfies three criteria:
- It doesn’t interfere with other systems
- It’s not susceptible to emission from other systems
- It doesn’t cause interference with itself.
To prevent the product from transmitting and receiving undesired signals, it’s recommended that the product be shielded. Shielding generally refers to a metallic enclosure that completely encloses an electronic product or portion of product. However, in most cases having the outer layers filled with ground plane serves the shielding purpose as it absorbs energy and minimizes interference.
Via in pad for ultra-fine pitch
When using the via-in-padtechnique for BGA signal escape and routing, vias are placed directly onthe BGA pads and filled with conductive material, usually silver, thatprovides a flat surface.
The micro BGA via in pad fan-outexample used here is based on 0.4 mm ball or lead pitch and the PCB is18 layers, including eight signal routing layers. A greater number oflayers is usually required for BGA routing. But in this example, thenumber of layers isn’t an issue since fewer number of BGA balls areinvolved. Still, the key issue is the micro BGA’s narrow pitch of 0.4mmwith routing not permitted on the top layer, except for fan-outs. Thegoal is to fan out the micro BGA without adversely affecting PCBfabrication.
Figure 5 shows the footprint from the BGAdevice’s manufacturer. As can be seen, the recommended pad size is 0.3mm (12 mils), and pin pitch is 0.4 mm (16 mils). It’s not possible tohave the traditional dog bone fan-out pattern due to the extremely smallspace between the pads. Even a small size via cannot be used for a dogbone fan-out strategy; here a small size via means 6 mil drill and 10mil annular pad. Another important mechanical limitation is boardthickness, which is 93mils.
Inthis case, the easiest solution is using micro-via-in-pad. However,micro-via size cannot be more than 3 mils. But the 93 mils boardthickness is a limiting factor. Another option is blind and buried viatechnology. These options will limit manufacturing choices and increasecosts.
To have the option of going to different fabricationhouses, drill size in a 93 mils thick board cannot go smaller than 6mils, and trace width cannot be smaller than 4 mils. Otherwise, only ahigh end, exclusive board manufacturer can handle this project, at apremium. Figure 6 shows the BGA footprint associated with this example.
Figure6: This fan-out method avoids using a high-end technique and doesn’tjeopardize signal integrity. BGA pins are divided into two sections asfar as internal and external pins.
The fan-outmethod shown in Figure 6 avoids using a high-end technique and doesn’tjeopardize signal integrity. BGA pins are divided into two sections asfar as internal and external pins. Via-in-pad is used for the internalsection, while external pins are fan-out at a 0.5mm grid. Figure 7a shows the top layer and Figure 7b shows top and internal routing layers.
Figures7a and 7b: Via-in-pad is used for the internal section, while externalpins are fanned out at a 0.5mm grid. Fig. 7a shows the top layer; Fig.7b shows top and internal routing layers.
SinceBGA pad size is 0.3mm (12mils) and pitch is 0.4mm (16mils), a 6/10milvia (hole/annular ring size) is used in the pads. The same via is usedfor external extended fan-out. For the internal section, clearancebetween vias is 6 mils, which is standard and doesn’t pose a problem atfabrication. For the external section, spacing between vias is 10mils. This spacing is used to run a 3-mil trace with a 3.34-mil distancefrom the vias. This particular strategy allows all signals from a 0.4mmpitch micro BGA to be successfully fanned out without complying withany special fabrication requirements.
The basic steps remain thesame whether using dog bone or via in pad, i.e. defining proper channelspace. It includes defining via hole and pad size, trace width,impedance requirements and stackup. However the difference lies in viaarrangement and the sets of vias that are used.
It is recommendedthat a blind/ buried via configuration up to six layers in depth beused. Going beyond causes fabrication yield issues. The preferredtechnique is to use staggered vias vs. stacked vias, as shown in Figure 8 .Staggered vias allow for more accurate registration tolerance asthey’re not mandated to align perfectly as required in the case ofstacked vias.
Figure8: Staggered vias allow for more registration tolerance, as they’re notmandated to align perfectly as required in the case of stacked vias.(Courtesy of IPC)
What can go wrong by missing these steps
Manufacturingand functionality are two key aspects that need to be consideredregardless of whether dog bone or via in pad is used. It’s critical toknow the manufacturing limits of the fab shop that will be used. Thereare shops that can manufacture extremely tight designs. However, if theproduct is going to volume production it gets very costly. It istherefore extremely important to design in a way that averagemanufacturing facilities can handle them.
To summarize, the key factors to consider from manufacturing perspective are
- Via – hole size (depends on aspect ratio)
- Via – annular ring (min 3 mils is required)
- Via – stacking (stacked vs staggered)
- Copper to copper space. (min 3 mil is recommended)
- Copper to drill space. (min 5 mil is required)
- BGA land size vs ball size for assembly.
Thereis always a tradeoff when it comes to manufacturability vsfunctionality. It is critical to analyze each properly and makecalculated decisions.
Functionality, on the other hand, includessignal integrity, power distribution, and EMC. These can be divided intoseveral main categories:
- Reflection and transmission line (one line) Key is impedance control. Impedance is controlled by trace width, dielectric thickness and reference plane.
- Cross talk (two or more lines) Spacing between traces on same and adjacent layer is key to control cross talk. Having ground layers between each signal layer, and ground shield traces around noise sensitive or noise emitting traces help minimize cross talk.
- Power distribution (rail collapse) This is inductance of power nets. Having power and ground planes adjacent and decoupling caps helps control power surges.
- EMI (system collapse) The controlling of all above elements and shielding the entire PCB or noise sensitive and generating portion helps control EMI.
Thisis true for the entire product. However, this is particularly true atBGA areas where all signal and power come in close proximity to eachother, thus making it challenging. Proper knowledge of signalcharacteristics help in making decisions as to which net has morepriority in terms of functionality.
Having a solid ground planein a layer adjacent to the BGA helps in tackling most signal integrityconcerns. One critical benefit of blind vias is that the stub length iseliminated in blind/buried vias, and this is extremely important forhigh frequency signals.
The technology of BGApackaging for embedded designs is steadily advancing, but signal escaperouting is difficult and challenging. Several major considerations areinvolved in selecting the correct fan-out/routing strategy: ball pitch,land diameter, number of I/O pins, via types, pad size, trace width andspacing, and stackup. Following the strategies outlined in this articleensures that a product is correct in terms of form, fit and function.
Faisal Ahmed is a PCB layout engineer at NexLogic Technologies, Inc. ,San Jose, CA. His design and layout experience spans 14 years, withemphasis on mixed signal and HDI. He received his BS degree inElectronics from NED University of Engineering and Technology KarachiPakistan.
Ishtiaq Safdar is a PCB layout engineer at NexLogic Technologies, Inc. ,San Jose, CA. He has been a board design and layout engineer for morethan 10 years. He has extensive experience working on PCB designspopulated with small packaging to include micro BGAs. He received hisBachelor of Engineering (BE) in industrial electronics from NEDUniversity of Engineering and Technology, Karachi, Pakistan.