Managing mixed voltage interfaces between portable devices and memory cards - Embedded.com

Managing mixed voltage interfaces between portable devices and memory cards

As portable applications become more feature-rich and smaller in formfactor, power consumption becomes critical in a design.

Advancements in process technologies have allowed designers to takeadvantage of the latest processors that operate at lower voltages.However, the side effect of using lower-voltage processors is often amixed-voltage system.

For instance, several processors have maximum I/O voltagesrestricted to 1.8V, with many of the peripheral devices continuing tooperate at more traditional voltage nodes (3.3V).

This also holds true with most removable flash memory cards, whichare often used in portable applications operating at 3V. To enableseamless communication between a low-voltage processor and a 3V memorycard, a voltage level translator must be used for proper interfacingbetween the two devices.

Figure1: Traditionally, the processor and SD/SDIO card both operated at thesame voltage level.

Traditionally, the processor and SD/SDIO card both operated at thesame voltage level. Figure 1, above ,shows the interface between the two devices. The SDIO interfaceconsists of four data signals (DAT0-3), one clock signal (CLK) and onecommand signal (CMD). The data and command signals are bidirectional,while the clock signal is unidirectional.

The card connector typically has mechanical write-protect andcard-detect switches. Their signals are sent back to the processor toimplement control functions such as powering up certain sections of theboard. To prevent data signals and the command line from floating,pull-up resistors to VDD must be implemented.

Table1: The system designer must consider trade-offs when choosing a leveltranslator for the SD or MMC interface.

With processors and SDIO peripherals now operating at differentinterface supply voltages, a level translator has to be added to ensureswitching compatibility. Several options are available to achieveproper voltage level translation and, depending on applicationcircumstances, one option may be preferred over another.

For example, system designers have multiple choices of leveltranslation solutions for controlling the bidirectional flow of dataand command signals from processor to card. Designers can either use alevel translating transceiver with a direction control pin, or use a”directionless” level translator. Both are viable options with variousbenefits and potential drawbacks.

Figure2: Fully buffered translator has output transistors that offer severaltens of milliamps of DC current with data rate restricted only by theoutput capacitive load and switching speed of the transistors.

Direction control pin
Figure 2, above, shows abidirectional translator with a direction control pin or “fullybuffered” translator. The output transistors are typically sized tooffer several tens of milliamps of DC current, and the data rate isrestricted only by the output capacitive load and switching speed ofthe transistors.

The fully buffered voltage translation solution is shown in anSD/SDIO interface application (Figure3 below ).

Figure3: One drawback of the fully buffered solution is the multipleprocessor GPIOs needed for the direction signals that control the dataand command lines.

One obvious drawback of this fully buffered solution is the multipleprocessor GPIOs needed for the direction signals (DAT0-dir, DAT123-dirand CMD-dir) that control the data and command lines. The additionalsoftware programming required to properly set the processor signals mayalso be a disadvantage of implementing this method of leveltranslation.

However, there are several advantages to using a fully buff- eredsolution in this application. Card specifications such as MMC 4.1indicate that a clock can run at a frequency as high as 52MHz with eachdata bit running at a maximum rate of 52Mbps. SD cards can operate witha clock frequency of up to 50MHz in the high-speed mode.

Figure4: A 52MHz clock and 52Mbps data signals pass through a fully bufferedvoltage translator.

These card specs also indicate that edge rate of the clock signalmust not take slower than 3ns. Thus, fully buffered solutions must beconsidered, given that other solutions have restrictions on maximumallowable frequencies and may violate the edge rate requirements on theclock signal.

Figure 4 above shows a 52MHzclock and 52Mbps data signals passing through a fully buffered voltagetranslator.'Directionless' level translators
Bidirectional translators that do not require a direction controlsignal are called “directionless” translators. The obvious advantagesof this solution over the previous one are processor GPIO savings andsimpler software coding requirements. Directionless translators havetwo topologies: an auto direction-sensing topology (Figure 5 below) anda FET based topology.

Figure5: The auto direction-sensing translator has a restriction on themaximum DC current load that can be connected at its outputs.

The auto direction-sensing translator has a restriction on themaximum DC current load that can be connected at its outputs. In a DCstate, the output drivers can maintain a high or low state with a verylight resistive or high impedance load. The output drivers are designedto be weak, so they can be overdriven by an external driver when datastarts flowing in the opposite direction.

Due to its weak DC drive (about tens of microamperes), these devicesmust be used carefully in applications where pull-up or -down resistorsare present on the data I/O lines.

To maintain fast output edge rates, output one-shots are used toprovide a strong AC drive. The maximum output frequency of thesetranslators is restricted by the amount of time that the one-shots aredesigned to stay turned on. For instance, a oneshot designed to beturned on for 10ns will allow a maximum frequency equal to 1/(2 * 10ns)= 50MHz.

Figure6: TXB0108 auto direction-sensing translator is used to interface withan SD/SDIO card.

The following are considerations when using an auto direction-sensing translator in a memory card interface application:

1) To prevent floating buslines, card standards recommend adding pull-up resistors on the dataand command lines.

When using an auto direction sensing translator, the value of thesepull-up resistors must be kept high enough to ensure that they do notcontend with the weak outputs of the translator. For card interfaceapplications using auto direction- sensing translators, the highestallowable pull-up resistor value of 100k ohms must be used.

2) For MMCs, the CMD linesignal is initialized in an open-drain mode and later shifts into apush-pull mode. The auto direction-sensing translator is intended foruse with a pushpull driver only and must not be used with open-draindrivers.

This is because the auto direction-sensing devices have an inputcurrent requirement. When applied with an open-drain driver, the weakpull-up resistor on the bus is unable to fulfill this input currentrequirement. Thus, these auto direction-sensing translators must not beused to interface with MMCs.

Figure 6 above shows theschematic for using an auto direction-sensing translator to interfacewith an SD/SDIO card. Figure 7 below a shows the clock and data signalsbeing translated from 1.8V to 3V using an auto direction-sensingvoltage translator.

Figure7: Clock and data signals are translated from 1.8V to 3V using an autodirection-sensing voltage translator.

Meanwhile, the FET-based topology is another “directionless”solution. This translator uses a pass transistor FET structure withinternal pull-up resistors on both sides. Speed-up circuitry isintegrated to improve the output slew rate of the translator.

Figure8: Translator uses a pass transistor FET structure with internalpull-up resistors on both sides. Speed-up circuitry is integrated toimprove output slew rate.

Due to their internal structure, these devices can be used withpushpull and open-drain drivers. This is a practical solution tointerface with an MMC or with a slot that is designed to accept bothMMCs and SD cards.

Figure9: An 8bit FET-switch translator is used to interface with a slotdesigned to accept SD/SDIO and MMCs.

Figure 9 above shows how an8bit FET-switch translator is used to interface with a slot designed toaccept SD/SDIO and MMC.

Figure 10 below shows a25MHz clock signal and a 25Mbps data signal being translated from 1.8Vto 3V using the FET-switch translator.

Figure10: A 25MHz clock signal and a 25Mbps data signal being translated from1.8V to 3V using the FET-switch translator.

Multiple options
For SD/SDIO or MMC interface applications, system designers havemultiple options for voltage level translation between the coreprocessor and the cards. In interfacing these cards with the processor,fully buffered translators offer high data rates and do not placerestrictions on the values of pull-up or pull-down resistors connectedto the data and command I/Os.

However, these devices need a direction control signal to controlthe data and command flow from the processor to the card and viceversa. Auto direction-sensing translators eliminate the need for thesedirection control signals. Pull-up or -down resistors on the bus mustbe chosen carefully for this solution to work correctly.

In addition, these translators cannot be used with open-draindrivers. They are not an option for interfaces with MMCs, since the MMCcommand line is initialized in an open-drain mode. FET-switchtranslators can be used to interface with MMCs and SD/SDIO cards.

However, FETswitch translators typically support lower data ratesand place a restriction on the maximum operating frequency of thesememory cards. The system designer must consider these trade-offs whenchoosing a level translator for the SD or MMC interface.

Prasad Dhond is Senior Marketing Manager, Standard Linear andLogic Products, Texas Instruments Inc.

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