Managing power consumption on your portable applications processor design - Embedded.com

Managing power consumption on your portable applications processor design

Power management solutions for today's portable applications processorsare becoming highly integrated. Total power consumption, standby anddeep-sleep current consumption affect battery size, bill of materials (BOM) cost and productacceptance.

System designers must consider many variations of power supplieswhen designing portable devices such as smart phones or PDAs. As theyget more power-hungry, smart phones require highly integratedpower-management solutions to achieve the overall design goal ofmaximum battery life in the smallest PCB area possible.

Today's applications processors require separate power domains forthe core, I/Os, memory and peripherals. The LP3971, for instance, is apower management unit (PMU) designed to meet all ofthese requirements using three high efficiency buck converters and sixlow dropout (LDO) regulators.

Applications processors require multiple power-supply voltages,which can be optimized as demanded by the core power manager and systemarchitecture. LP3971 meets a wide range of system requirements with I2C controlled output voltages,factory-configurable power-on sequencing and default output voltages.

This article focuses on powering a microprocessor's low voltage railin a PDA/smarphone application using devices such as the LP3971 whichcombine buck converter and LDO functions.

When designing a system, the architect must balance suchrequirements as cost, PCB area, component size, talk time, standbytime, battery capacity and schedule. The microprocessor RAM requires a1.5V supply with a maximum current of 400mA. Let's start with thesimplest, lowest-cost solution – an LDO regulator connected directly tothe Li-ion battery (Figure 1, below ).

Figure1: The simplest, lowest-cost solution for an applications processor isan LDO regulator connected directly to the Li-ion battery.

The battery voltage will start at 4.2V and decrease to 3.2V, wherethe system enters into deep sleep until the battery is recharged orreplaced. Figure 2 below showsa typical Li-Ion battery discharge cycle.

For the configuration shown in Figure1 , the efficiency of LDO 5 will be: LDO percent efficiency = [(Vout * Iout ) / Vin * (Iout + Iq )]* 100. For this and all other examples in this article, Iq is removed because it is very low (40 microAmps) compared with Iout (400 milliamps).

The efficiency equation then becomes:

Percentefficiency = [(V out )/(V in )] * 100.

For Vin = 4.2V and Vout = 1.5V, the LDOefficiency is 1.5/4.2 = 36 percent. Total power is Pt = 4.2* 0.400 = 1.70W.

Figure2.A typical Li-ion battery discharge cycle.

All power that is not delivered to the output load is dissipated asheat within the LDO. Dissipated power is estimated as:

Dissipatedpower(P d ) = (V in – V out ) * I out = (4.2 – 1.5) * 0.400= 1.1W, dissipated as heat.

We have just calculated the maximum continuous power (Pt ).RAM will not operate at this level for very long. If we look at a 10percent duty cycle, the average power consumption will be:

P t =0.10 * 1.7 = 0.17W.

The amount of time the RAM operates at Imax depends on theapplication, power-management firmware and OS. In Figure 2, the batteryvoltage does not stay at 4.2V for long. At a nominal battery voltage of3.6V, Vout is still at 1.5V; the LDO efficiency is 42 percent.

Figure3. The input of LDO 5 is connected to the output of buck 3, which isset at 1.8V to power memory.

If the system requires lower power consumption and theconfiguration in Figure 1 is not acceptable, consider the solutionshown in Figure 3, above wherethe input of LDO 5 is connected to the output of buck 3, which is setat 1.8V to power memory. For the configuration shown in Figure 3, whenthe input of LDO 5 is connected to a 1.8V rail, the efficiency iscalculated as:

Efficiency = V out / V in = (1.5V/1.8V) * 100 =83 percent.

Dissipated power is estimated as:

P d =(V in – V out ) * I out = (1.8 – 1.5) * 0.400 = 0.12W, which will be dissipated as heat.

The LDO 5 efficiency is 83 percent. Note that if we were to use aswitching supply instead of LDO 5, the efficiency could be as low as 85percent – an improvement of just 2 percent for this block. However,overall efficiency depends on the type of converter that is used.

Using the efficiency curves from the LP3671 buck converter datasheet(Figure 4, below ), the overallsystem loss due to this double conversion DC/DC + LDO will be 78percent. An LDO is the lowest-cost, smallest-size and lowest-noisesolution.

Figure4. Using these efficiency curves, the overall system loss due to thisdouble conversion DC/DC + LDO will be 78 percent.

Adding another DC/DC converter to power the RAM will increase thePCB area due to the addition of a very large external inductor (3mm x3mm) by 10 mm2 and increase the overall noise of yoursystem. If a 1.8V supply is not available, any buck converter voltagerail that is lower than Vbatt can be used. The lower the LDOinput voltage, the higher the efficiency – as long as the input voltageis above Vout + Vdropout .

There is no reason to worry when using an LDO to power low-voltagemicroprocessors. Ask yourself: “Do I really want to use an extra buckconverter and inductor to improve system efficiency by just a fewpercent?”

Using a buck converter to power the low-voltage rails will increasethe size of the power management IC, add another 3mm x 3mm inducto, andincrease the BOM cost and PCB area. In contrast, an LDO is inexpensive,small and easy to use. It is also the lowest noise solution that can beoptimized for your application.

Ken Marasco is a System Architectat National Semiconductor Corp.

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