The widening gap between power and performance requirements of applications and what is afforded by technology scaling and architectural techniques clearly points to multiprocessor architectures as the solution. For example, even the present day wireless standard 802.11a requires more than 5 GIPsof conventional DSP processing for its physical layer.
The challenge going forward is to be able to sustain several applications that are at least an order of magnitude more demanding than the 802.11a, like 802.11n,802.11m. Memory dominates the cost, power and performance of heterogeneous multi-processor architectures.
The need for largeamount of storage and a high bandwidth access to it comesfrom two ends. The primary need comes from the applications becoming more complex and data intensive (high resolution,higher bandwidth communication etc.). The secondary need comes from the requirement to hide the latency of accessing slower off chip memory.
To comprehensively optimize both the aspects, the challenge is to treat the memory question at system level where decisions are made about how to map complex and abstract data structures to efficient distributedmemory hierarchy and provide runtime support for memory management and scheduling.
MOSART addresses two main challenges of prevailing architectures:
1) The global interconnect and memory bottleneck due to a single, globally shared memory with highaccess times and power consumption; and,
2) The difficulties in programming heterogeneous, multi-core platforms, in particularin dynamically managing data structures in distributed memory.
MOSART does this through the use of a multi-core architecture with distributed memory organization, a Network-on-Chip(NoC) communication backbone and configurable processing cores that are scaled, optimized and customized together to achieve diverse energy, performance, cost and size requirements of different classes of applications.
MOSART achieves this by: (1) Providing platform support for management of abstract datastructures including middleware services and a run-time data manager for NoC based communication infrastructure; and (2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
**Other authors who contributed to the report are Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris at Iroon Polytechnic in Greece; Xiao wen Chen, Jean-Michel Chabloz, Ahmed Hemani, and Axel Jantsch, Royal Institute of Technology, Sweden; Geert Vanmeerbeeck, IMEC, Belgiuim; Fragkiskos Ieromnimon and Dimitrios Kritharidis,Intracom S.A., Greece; Andreas Wiefrink and Bart Vanthournout, Synopsys, Belgium; Jari Kreku and Kari Tiensyrja, VTT Platforms, Oulu, Finland; and Philippe Martin, Arteris, France.
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