SAN FRANCISCO — Engineers need new interconnects and memory architectures to lower the cost and complexity of next-generation chips and systems, said the chief executive of Marvell Technology Group in a keynote at the International Solid-State Circuits Conference (ISSCC) here.  Sehat Sutardja promised to roll out prototype chips before the end of the year based on the MoChi interconnect and Final-Level Cache memories he is helping design.

The initiatives could help Marvell differentiate its chips with packaging and software techniques it can control while facing rising costs of making chips. Given the need for multiple-patterning lithography, a mask set for a new chip design will cost $10 million by 2018, Sutardja projected, a figure some would consider a low estimate.

“The steep rise in mask costs is finally taking its toll on the bottom line for companies including Marvell,” he said.

Marvell CEO Sutardja brought a Silicon Valley look to the normally formal ISSCC. (Photo credit: EE Times/Rick Merritt)

Marvell’s pending MoChi interconnect is based on the ARM AXI link running at 8 Gbits/second or faster to keep chip-to-chip latency low. MoChi links can daisy-chain multiple chips together and can use micro-serdes and low-swing differential signaling.

The company is already in negotiations to license MoChi to an FPGA maker and several partners in Japan. However, it has no immediate plan to make MoChi an industry standard.

“We are only licensing to partners close to us…if we make it too widely available it creates confusion because there are a lot of enhancements we are still working on,” Sutardja said in an interview after his keynote.

Marvell is keeping its Final-Level Cache technology even closer to its chest. FLC aims to radically reduce the amount of DRAM main memory needed in a system, replacing it with a small layer of high-speed DRAM cache and storage in solid-state drive.

Sutardja said FLC could cut the main memory needed in a system by as much as a factor of ten, promising lower cost, lighter and higher performance products. He described the technology as a kind of virtualized memory approach initially reserved for sale to his OEM customers.

“It’s a closed system for now, we will not license it for quite a while because the value is in the system,” he said.

Marvell's FLC reduces DRAM footprint, relying more on SSDs and hard disks

To read more of this external article, go to “Mixed reactions for MoChi, FLC. “